Component Ground Plane and Trace Keepout Areas

I am a novice with KiCad. I have done a layout of a board to do prototyping that has empty sockets with no designated components. There is a pwr supply section with 3 caps 2 voltage regulators, 2 resistors, 2 leds and a barrel pwr connector. There is no schematic because it is not necessary, and how to show numerous unpopulated headers is not clear.
I used to design PCBs in the old days using Bishop Graphics red and blue tape and so I am used to simply jumping into the layout phase of PCB design with or without the help of a paper logic drawing.
I have previously used Fritzing and while it is very limited compared with KiCad it has a useful feature that allows the user to designate pads as ground fill seeds so they will be connected to the bottom side ground plane copper. Undesignated bottom side pads and traces are automatically considered ground plane keepout areas.
Is there any easy way to designate bottom side pads and traces connecting them to be keep out zones for the bottom side copper fill? I have searched the forum and the only thing I see is the creation of a netlist from a schematic (a thing that I do not have) which seems to be several orders of magnitude more complicated than simply designating pads and traces connecting them to be keep out areas for bottom side ground plane copper (or the opposite of designating bottom side connection pads as ground so as to be included in the ground plane copper fill).

I don’t fully understand the second point, but I think it can be easily solved. About the first point: this seems to be a never ending discussion. There are probably hundreds of threads here which either start with this discussion or end with it. There are so many of them that it feels unnecessary to even try to find a few links. They all end up recommending creating a schematic, with good reasons.

If you want to use KiCad (or any other EDA) with better capabilities than Fritzing, just learn to use the schematic. If you learn that, it will take almost less time to create a schematic for your board than it took to write your message.

KiCad (or any other full EDA package) is designed for schematic -> layout workflow. The unstable development version 5.99 (nightly builds) of KiCad supports schematicless designs, but still you need nets. Even the small amount of components make it more feasible to create a schematic if you are going to use KiCad further and espcecially if you want to learn to use it for more projects.

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I completely agree with eelik.
Trying to work without a schematic is more complicated then making a schematic.

In KiCad everything starts with the schematic, which is what generates the netlist, and without a netlist you can’t do much.

You say you also have a few capacitors and voltage regulators. You probably want to connect those to each other, and also to some power input connector. This sounds like a real good reason to me to draw a schematic.

In KiCad it mostly works the other way around.
For complicated PCB’s a schematic and netlist is quite usefull, not even a discussion. For very simple PCB’s (even e few netlist connections) a schematic is so trivially simple to draw there is no reason not to do it.

Definitely, draw the schematic first …

OK, I can tell when I am outnumbered (and I really do appreciate all of the comments which I know are meant to be helpful). I will bite the bullet and try the schematic. One question: how do you represent three unpopulated DIP IC sockets on a schematic, each of whose pins are connected to a a different pin on two separate headers? This is mostly what I am not sure of.

In KiCad there are two diffferent sort of components.
There are “fully specified” componens, which have already a footprint assigned to the schematic symbol (Schematic symbol is the “main reference” for a part), and there are generic parts, which do not have any footprint assigned. For parts like resistors, capacitors and diodes, there are just a few schematic symbols, but there are thousands of different footprints for those. KiCad is built to handle this. Any footprint can be assigned to any schematic symbol.

If you want to do it fancy you can design a schematic symbol (quite simple, but it takes some getting used to). If you want a quick and dirty solution, just grab a connector symbol with the right number of pins.

For example;

  1. Start eeschema.
  2. press: “a” (for add schematic symbol).
  3. type: image

This is an abbreviated search for all of the (partial) terms above. In practice it shows results for connectors with 2 rows and 8 pins for each row.

Once you’ve placed such a connector symbol, you need to assign a footprint to it. Footprints are generic parts, for example for a DIP16 or a TQFP100. There is no such thing as a footprint for a “TL074”.
Assigning footprints can be done in several ways, so time for some reading. (If you’ve already placed some footprints on a PCB, then you know how to find them)

I’m not sure how to interpret this:

Can you draw a schematic of it? :slight_smile:

I think you want to use 3 connector symbols. One for your DIP socket, and two for your headers, and then draw wires between them.

Try pressing the [Ins] key after you drew a horizontal wire. It will repeat your action.

I’ve been tinkering a bit.



3D view:

The Project: (6.0 KB)

[Edit] I made a mistake, and drew the PCB outline on the wrong layer. I moved the lines to the Edge.Cuts* layer, and uploaded a new zipped version of the project. (With added time: “T04:43”) The lines now look yellow in Pcbnew.


I came to a similar result in the schematic. How did you get what is identified as a “connector” in the schematic to become a DIP package in the layout? I apologize in advance if this is a stupid question. How can I send you my schematic so you can see what my bumbling came up with?

New forum users have to accumulate some “viewing time” before they can upload files. It’s an automated anti-spam feature.

The FAQ part is an excellent place to do some reading. It is currently the most up to date collection of tutorials about specific KiCad features.

As I wrote before, you can add any footprint to any schematic symbol.
One way of assigning footprints is: Eeschema / Tools / Assign Footprints

I choose “Socket Longpads” (in DIP16 variant) (I also could have chosen an DIP 40, but those are big.

The 3D model you get for free. It is linked to from the footprint, and you can preview your PCB with: Pcbnew / View / 3D Viewer

Hi, Kend

I agree with the others here regarding drawing the schematic. But I don’t see any indication as to whether you understand layout of (switching or linear) voltage regulators. I will repeat my old refrain drawn from 40 years of power supply design: Something like this: “I know of no power supply design which is so simple that it cannot be significantly degraded by bad pcb layout.” One of the simplest power supply designs uses a 7805 type linear regulator chip. I have seen a 7805 regulator board which exhibited high ripple due to bad layout. On the opposite end of the spectrum, I have also tested a pcb using an ST switching controller chip. The board had no netlist errors but the layout was so bad that I was unable to get the slightest blip of power out of it. Do you know what you need to know regarding proper pcb layout of your power supply?

Hi Bobz,

I am using linear regulators. I have built them before on 0.1 grid hole pc board with e.g., 7805 and have never had a problem. I am interested in your thoughts on what is a good layout. I have +7.5V going from a barrel pwr connector into a LD1117S50 giving me +5V and the +5V goes into a LD1117S33 giving me +3.3V. Planning on 220µF and 0.1µF bypass at each of the +7.5V, the +5V and the +3.3V. If you think placement is somewhat critical I am eager to have your thoughts.

Hi, Kend

I will list a few pointers: I was not familiar with “LD1117” but found the ST Rev 37 datasheet on DigiKey website. I will refer to the application circuit figure 4.

  1. A wide ground plane (I think you are doing that) is a good idea. But if the layout has any visible direction of current flow, the ground current should flow from the input source to (Cin and the LD1117 chip and Cout) and from there to the load.

  2. Cin and Cout should be connected close to the chip and close to its ground pin. The bad design I remember was powered by a mains frequency transformer, bridge rectifier, and input bulk filter capacitor. There was a ground trace running from the bridge rectifier to a large value Cin. Cin needed to be large so as to filter 100 Hz or 120 Hz ripple. Cout was probably grounded close to Cin. The 7805 ground pin had a trace going to the bridge rectifier and was not connected at Cin. Pulsating current from the bridge to Cin caused ripple voltage to appear across the length of that ground trace. The result was significant ripple in Vout.

  3. Taking items in date-context; I am not sure when the LD1117 was introduced but it may be only slightly newer than the LT1117, so probably before 1990. The main question is what type of capacitor to use at Cout. These days most new designs would use a chip ceramic, but LD1117 may become unstable with such low ESR. So the safest choice there would be a low ESR (polymer or aluminum electrolytic) type. Looking at aluminum types at DigiKey, I would probably choose something with 0.1 to 0.2 ohms of ESR (or impedance) for 220 uF. A 10 uF low voltage electrolytic is pretty small and you might choose 1-2 ohms impedance for that smaller value.

4: ADDED: Also…Unless you are squeezed for space, make your traces wide. In this low voltage circuitry, narrow traces have no electronic advantage relative to wide ones. You can probably use trace widths (not discussing the ground plane) that are somewhere between 1 - 5 mm wide depending on current… Not to say this is absolutely necessary, but it may help your output voltage regulation and will not hurt.

Thanks very much. Everyone here is extremely helpful.

Everyone here is incredibly gracious and helpful.
This helped a lot. I have assigned footprints to all components.
I then used the Eeschema / Tools / Update PCB From Schematic command and got a layout that is a jumbled mess with all components crammed together abutting each other and wires every which way. I am confident that the wiring connections are probably correct but . . . . how do I deal with this mess? Do I just sort it out one component at a time?

Revision list in LD1117 goes back to 2005.
It also states it has an NPN BJT as pass transistor, so it’s not the typical low-drop regulator.

Would you suggest that I use something else for the 2 regulators?

There are various ways to do the initial sorting.
I have a dual monitor setup, and sometimes I look at the RefDes (“Reference”) on the schematic and use the t shorcut key and type the RefDes of the part I want. Advantage of this is that the footprint can come from anywhere on the PCB and you do not have to zoom out.

Sometimes I make rough groups of stuff that goes together. Partly gleaned from the schematic, and partly from where the ratsnest goes.

You can try: Pcbnew / Place / Place Footprints Automatically…

But it will take some time to get a workflow that suits you.
For your first few designs, do not focus too much on getting it done. Spend some time on learning KiCad, browse throug menu’s, try some buttons, read some tutorials, watch Youtube movies if that’s your thing.

The wires every which way are called the “rat nest”.
This rat nest shows each and every wire connection you made in the schematic.
There is lots of information in the PC section of Help / Getting started in Kicad.

Rat nests can be very distracting when you first start your PC board. They can be toggled on and off with an icon on the left side of your screen… explore.

The method for laying out a board that works for me is:
1/ Turn rat nest off.
2/ Move components to where I want.
3/ Turn rat nest on.
4/ Rotate or move components to eliminate rat nest wires crossing each other.
5/ Return to schematic to see if changes there can eliminate last rat nest crossings
6/ Update PC from schematic.
7/ Repeat 1 - 6 as necessary.
8/ Replace rat nest wires with copper tracks.




I figured it out and moved components around. It sorted itself out.


It does that… sometimes