Circuit not parsed

Hey guys, I’m new to KiCad, and I can’t understand the problem

Note: No compatibility mode selected!
Circuit: KiCad schematic
Error on line:
i.xu1.i2 xu1.n005 0 1m load
unknown parameter (load)
Error: circuit not parsed.


I suspect the question has to do with simulation, is that right?

Yes that is the problem and I can’t find the reason.

Hello @JGB

Before you attempt simulation you need to fix some problems with the schematic.

eg. What are Q1 & Q2 doing?
According to data sheet:
Pin 11 of U1 is an open collector output.
Absolute min.voltage for Vcc is 10.
I don’t see pin1.

May well be more problems but the circuit posted is very hard to read.

thank you for your help.
I have export my circuit to clipboard, so it is more clear.
Q1 and Q2 is a noise generator
P11 of U1 has a 1u capacitor
pin 1 of U1 is grounded

The error message gives some hint:
i.xu1.i2 xu1.n005 0 1m load
is a current source (first character: i). The definition of a current source in a spice netlist is:
iname node+ node- value.
You have an additional token ‘load’. ngspice does not know what you (your circuit, the model, the netlist) intend to do with it, so it bails out.

Where is the current source put into the netlist? Its name is i.xu1.i2, so it is a source i2 in the device xu1, derived from u1. So it must be there in your model of u1, the xr2206. Is there a bug in the model? Is there a ‘feature’ not supported by ngspice? I cannot check this unless you post your project, including the external models.

A good engineering practice is to separate the problem, if you have no clue in the beginning. You have a circuit with 3 building blocks. Try to simulate them separately (triangle, noise, amplifier).

Thanks for the help again, but the problem is still here.

I post the subcircuit of xr2206 if it can help
there is a load in it but I cant understand what is wrong.

  • XR2206CP-F.asc V0.9
  •         1   2   3  4   5   6   7   8    9   10   11    12  13    14    15    16

Q1 N033 N023 N040 0 NPN1
Q2 TC2 N023 TR1 0 NPN1
Q3 TC1 N022 TR1 0 NPN1
Q4 N034 N022 N040 0 NPN1
Q5 N014 N033 TC2 0 NPN1
Q6 N015 N034 TC1 0 NPN1
Q7 N014 N009 vo 0 PNP1
Q8 N022 N014 N009 0 PNP1
Q9 N015 N009 vo 0 PNP1
D1 vo N009 DD1
Q10 N023 N015 N009 0 PNP1
D2 N015 N014 DD1
D3 N014 N015 DD1
D4 N023 BIAS DD1
D5 N022 BIAS DD1
R1 TR1 GND 20k
R2 N025 N033 4k
R3 N025 N034 4k
D6 N018 N025 DD1
D7 vo N018 DD1
V2 N013 vo 0
C1 TC2 TC1 10n
R4 N022 BIAS 1e6
R5 N023 BIAS 1e6
Q11 N010 N023 N029 0 NPN1
D8 VCC N010 DD1
Q12 N010 N022 N030 0 NPN1
Q13 N039 N035 N029 0 PNP1
Q14 N037 N035 N030 0 PNP1
D9 N039 GND DD1
Q15 N037 N039 GND 0 NPN1
Q17 N035 N010 VCC 0 PNP1
Q18 WAVE2 N047 SYMA1 0 NPN1
Q19 WV1 N047 SYMA2 0 NPN1
Q20 VCC N016 WAVE2 0 NPN1
Q21 VCC N017 WV1 0 NPN1
R7 SYMA1 GND 2.2k
R8 SYMA2 GND 2.2k
Q22 N027 WV1 N041 0 NPN1
Q23 N026 WAVE2 N042 0 NPN1
R9 N041 N053 500
R10 N042 N053 500
Q24 N031 AMSI N043 0 NPN1
Q26 N002 N026 N031 0 NPN1
Q27 N003 N027 N031 0 NPN1
R12 N043 N052 1.3k
Q28 N032 N038 N044 0 NPN1
Q30 N002 N027 N032 0 NPN1
Q31 N003 N026 N032 0 NPN1
R14 N044 N052 1.3k
D14 VCC N011 DD1
D15 N011 N020 DD1
R13 AMSI N052 1G
R15 VCC N038 5k
R16 N038 GND 5k
Q25 N020 N020 N027 0 NPN1
Q29 N020 N020 N026 0 NPN1
Q34 N048 N021 N019 0 PNP1
Q35 N048 N048 GND 0 NPN1
Q36 N045 N048 HND 0 NPN1
Q37 MO MO N045 0 NPN1
Q38 N024 N024 MO 0 NPN1
Q39 N024 N021 N008 0 PNP1
Q40 VCC N024 N028 0 NPN1 5
R17 N028 N036 50
R18 STO N036 450
Q41 GND N045 N036 0 PNP1 5
Q42 N066 FSKI GND 0 NPN1
Q43 N064 N066 N068 0 NPN1
R23 N056 N066 10k
D10 N071 GND DD1
D11 N068 N071 DD1
D12 N057 N064 DD1
R24 N056 N057 5k
Q44 N056 N057 TR1 0 NPN1
R25 TR1 GND 1g
D17 N058 N065 DD1
R27 N056 N058 5k
Q48 N056 N058 TR2 0 NPN1
R28 TR2 GND 1g
D18 N070 N072 DD1
D13 N072 GND DD1
Q47 GND N066 N067 0 PNP1
Q49 N065 N062 N070 0 NPN1
R29 N056 N067 10k
Q46 TC1 N022 TR2 0 NPN1
Q45 TC2 N023 TR2 0 NPN1
R26 TR2 GND 20k
Q50 N062 N067 N069 0 NPN1
D16 N069 GND DD1
R31 N056 N062 10k
R32 N056 N069 50k
R33 N056 N070 50k
Q51 GND N063 BIAS 0 PNP1
Q52 N056 N061 N063 0 NPN1
R30 N063 GND 5k
B1 N060 GND V=limit(0,0.32V(VCC,GND),3.07)
R38 N060 N061 100
C3 N061 GND 100p
B2 N013 GND V=limit(0,0.7
B3 N046 GND V=limit(0, 0.25*(V(VCC,GND)-5),1.75)
R39 N046 N047 100
C4 N047 GND 100p
V1 N059 N056 0
B4 N059 GND V=limit(0,0.41*V(VCC,GND),5)
Q53 N040 N050 GND 0 NPN1
R40 vo BIAS 50k
R41 N053 GND 1e7
Q55 N055 N055 GND 0 NPN1
Q56 N053 N055 GND 0 NPN1
B6 GND N055 I=limit(0,(V(VCC,GND)-5)*0.8m,1.5m)
Q57 N054 N054 GND 0 NPN1
Q58 N052 N054 GND 0 NPN1
B5 GND N054 I=limit(0,(V(VCC,GND)-5)*1m,3.5m)
Q59 N051 N051 GND 0 NPN1
Q60 N035 N051 GND 0 NPN1
B7 GND N051 I=limit(0,(V(VCC,GND)-5)*0.05m,.16m)
Q61 N050 N050 GND 0 NPN1
B8 GND N050 I=limit(0,(V(VCC,GND)-5)*0.05m,.189m)
Q54 N019 N003 VCC 0 PNP1
Q62 N008 N002 VCC 0 PNP1
Q32 N002 N002 VCC 0 PNP1 4.5
Q33 N003 N003 VCC 0 PNP1 4.5
D19 VCC N004 DD1
D20 N007 N012 DD1
D21 N004 N007 DD1
R42 N021 GND 15k
I1 N012 N021 -3m
R43 N012 N021 100
Q63 N001 N001 VCC 0 PNP1
Q64 N008 N001 VCC 0 PNP1
Q65 N049 N049 GND 0 NPN1
Q66 N045 N049 GND 0 NPN1
B9 N001 N049 I=limit(0,(V(VCC,GND)-5)*0.15m,0.5m)
R45 WAVE2 WV1 100k
I2 N005 GND 1m load
I3 N006 GND 1m load
R11 WAVE2 WV1 180g
Q67 VCC TC1 N005 0 NPN1
Q68 VCC TC2 N006 0 NPN1
R47 N005 N016 500
R48 N006 N017 500
R49 N016 N017 400
.model DD1 D(Is=1e-15 Rs=10 Cjo=1p)
.model NPN1 NPN(Is=1e-15 BF=100 Cje=2p Cjc=1p Rb=20 Re=2)
.model PNP1 PNP(Is=1e-15 BF=25 Cje=2p Cjc=1p Rb=20 Re=2)
.ends xr2206CP-F

Hello again
I just made comment the word load, and it is working…
Thank you anyone…

The ‘load’ token seems to be a LTSPICE-specific option. See Setting current source as active load in LTSpice - Electrical Engineering Stack Exchange. It is not (yet) supported by ngspice.

I was using LTSpice and the subcircuit was taken ready.

Do you know how can I split my circuits in two or three schematic pages

This topic was automatically closed 90 days after the last reply. New replies are no longer allowed.