Changing connectivity and reverting it does some strange things to the board

@Seth_h

Perhaps I should have started a new topic, but since you have already downloaded the design I though maybe here would be better.

If you wouldn’t mind, I found a troublesome reaction to a component change then unchange on that same board.
My sequence is:

  1. eeschema: reverse the polarity of D7 (by rotate + rotate)

  2. Pcbnew: Update PCB from schematic

  3. Pcbnew: reverse the orientation of D7 (by rotate + rotate)

  4. eeschema: realize the diode was originally correct so we rotate D7 back to its original position.

  5. Pcbnew: Update PCB from schematic

  6. Pcbnew: reverse the orientation of D7 (by rotate + rotate)

Now I should be back to where I started but in Pcbnew there are two ratsnest lines on a connected net. The only way I could get rid of them is to select the net ( using “I” ) press E then OK…

I am using my own power symbol however I tried again with a built in power symbol with the same result.

Now for a simple board like this, its not much of an issue. However if I were rotating an IC with many pins things might get dicey.

Running DRC might have also fixed your problem. (Your changes in eeschema coupled with changes on the pcb side meant that the connectivity information got out of date. Running DRC should rebuild it.)

I ran DRC and it did not fix it. Oddly enough it did not find unconnected nets but it did flag every pad on the affected net as “trace too close to pad” which in this case the trace was on the pad.

I seems like the net name derived from the power (flag?) was overridden by what would be the net name if the net had not been named.

John

When importing a changes to the connectivity from eeschema you will get some tracks connected to new nets. (you would already get an DRC error at this point.)

I assumed this would be fixed by running DRC after rotating your diode but it seems not to be the case. (I seem to remember DRC did such things in v4 but i could be wrong here.) Maybe report this as a strange behavior over at launchpad.

Yes, the connectivity is not immediate propagated. If you add a step 7. Update PCB from schematic, it should fix it.

What happens if you save the PCB and then close / re-open Pcbnew?
It should also redo the connectivity checks.

Can it be that the pads of your component loose alignment when rotating, and that confuses Pcbnew?

@Seth_h “update from schematic” does not help

@paulvdh Pads do not loose alignment.

What appears to happen is:

The net in question has a power flag(?) on the schematic in several places
image

If I rotate D7 on the PCB, then rotate it back (don’t need to touch the schematic) the net name is lost.


Selecting the net, editing it will put the power flag name back on that net. Afterwhich Kicad is happy.

John

Now I’m a bit curious about how you got the net 24Vac onto the tracks in the first place. Did you assign that in pcbnew or did it come in automatically from the import?

edit Regardless of the method, you can fix the issue by changing (in Libedit) your 24Vac symbol from a Power Output to Power Input.

None of the power flags in the “Power” lib suited this application.

So in symbol editor I exported one of the existing flags (+6V in this case)

I then imported it to a personal library. Changed the shape and value.

I used this in eeschema which carried through to Pcbnew. I would expect this as normal behavior.

John

The value is not what determines the resulting netname. The name of the invisible pin is what is responsible for that.

More details see the section about power symbols of Tutorial: How to make a symbol (KiCad v5.1.x)

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You may have accidentally changed it from Power Input to Power Output. The library version (current) has +6V as a Power Input. Together with the hidden flag, this causes it to make a global label.

This non-intuitive behavior will become explicit in v6.

Perhaps I’m not using the power symbol correctly. I don’t care about spice. Here I used a simple (in my mind) global with the benefit that the reader will know it is a power source. Here DRC gives an error for the right hand +5V. Connected to other pins but not driven by…

Should I just use a global label? It would work but it wouldn’t be nearly as intuitive.

Going to now say that this appears,to me, like a BUG.

now no longer have a net connection…

@JohnRob it seems something in the ERC has changed. Could you add a PwrFlag to either of the two “+5V” connections and report back?

Power Flag added, ERC throws no errors.

Seems like overly convoluted requirements. But I can’t complain the program(s) are great for converting a design to a PCB.

John

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@Sprig as explained to you in your original post: Nothing of importance changed in ERC (Yes error messages got cleaned up but that does not change the behavior.)

Please do not confuse new users with things if you yourself do not fully understand the subject matter.

Yes the power flag is not intuitive. Mostly because the powerflag is just another symbol instead of being a special thing like the “this pin is left unconnected on purpose” flag.

But having this check at all adds a lot to kicads power. eagle for example has no way to check if a IC is powered. This means one thing more that the user needs to check manually. (Eagle has a electrical type of power input but lacks the one of power output. Meaning it can not be able to check for this.)

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Now I see :slight_smile:

The other thing that threw me (off the correct path) was that every voltage flag in the “power.lib” is described as a Power Flag. Unfortunate description.

John

That is something i can fix. Will take me an hour or so.

Edit: pull request created https://github.com/KiCad/kicad-symbols/pull/1671

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Thank you.

I hope my issue was able to help others. As I said before I love Kicad. I’ve only been using it for a few months and I’ve just received my 3rd board. All 3 are pretty simple but useful. Its gotten so hand built prototypes (or in my case final usable device) is a thing of the past.

John

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Again, I agree that the PwrFlag in KiCad is a game changing solution to ERC checking.

But, can it be made to be hidden while printing/plotting the schematic onto paper?

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