@jmk I have now updated to 7.0.11 as suggested, and chosen the footprint from the library (Package_SO:MSOP-8_3x3mm_P0.65mm), but still the same problem.
@paulvdh pointed out the overlapping clearance lines, and they are still there with the new footprint. It seems that is the problem, but I can’t see where to change it.
Paul mentioned net-classes and perhaps that is it. Those overly-fat i2c traces perhaps have net class constraints that over-rode the default clearance. Peek at the pcb-setup/netclass dialog, or maybe try deleting those fat i2c tracks and the footprint and update from schematic again.
Partially solved at last. It is a Design Rules issue, but not the general minimum constraints. I needed a new Pre-Defined Size track of 0.3 mm width and 0.2 mm Clearance (I called it Fine), and then to make sure all the pads in that MSOP device had associated Net Classes which required that Fine track size.
Since there is a voltage pad (3v3) and a GND pad on that device, that is a problem, since other devices need larger currents on those lines, so my general setting had been for wider tracks and clearances.
But its only partially solved, because even having set the Design Rules for the 3V3 and GND net classes to my Fine track size, the clearance lines around those respective pads haven’t changed, and nor have any of the other pads whose Net Classes I have specifically set to the Fine class.
Just pad 5 the 3v3 pad allows the new track size. Pad 6 shows the acceptable clearance around it, but pad 7 GND still overlaps pad 6.
Is there any way to split a Net Class into different regions allowing different track/clearance sizes?
Does not compute:
PCB Editor/ File / Board Setup / Design Rules / Pre-defined Sizes does have a track width, but it does not have a clearance. I mentioned: PCB Editor/ File / Board Setup / Design Rules / Net Classes, and that is a different setting. (Very different indeed).
Net Classes are a set of rules, both for track width and clearance, and you can define in the schematic which net goes to which net class. This is the normal way of defining track width and clearance. The Pre-defined Sizes is only an extra setting that makes it easier to draw some tracks that deviate from the net class settings. Study the manual and/or tutorials until you understand how these net classes work. They are an important concept in PCB design.
Thanks @paulvdh. So ‘Pattern’ is all the connections to a particular node in the ratsnest. In the Settings, I can define which Netclass (which is a group of settings covering track width, clearance, via size, …) is assigned to each pattern.
Is there a difference between Net Class and Netclass?
Is it possible to split a set of connections for one node in the ratsnest into 2 different Patterns? I need some /GND tracks to be fine, and some to be wide, to carry different currents.
Presumably my MSOP footprint had no clearance conflicts when the schematic was first converted to a board layout. At some stage that changed without me noticing, and I don’t know how to revert. What action is likely to have caused that, and when taking that action, how could I have known that it caused the conflict? If I could ascertain that, I might be able to work out the steps to undo the conflict.
The only difference I see is with or without a space in between 
What is a “pattern”. I guess you mean a “net”. A net is a list of nodes (pins) that are connected together. A NetClass (Net Class) is a set of rules (track width, clearance).
In KiCad you can use net ties to split a net into sections. You can also use the pre-defined widths to make a track narrower. Or you simply draw a track somewhere on the PCB, hover over it and press e to edit it’s properties, and then change the width. If you then move the track and place it onto a pad, it will automatically become a part of the same net as that pad.
With the button below, you can switch between always using the netclass width while drawing a track, or continuing with the same width as a track that is already on the PCB when drawing tracks.
@paulvdh thanks for all your explanation on this.
Net Class, Netclass and Pattern all mentioned in the Board Setup view.
The list of Patterns becomes a list of Nets in the PCB Editor Appearance section:
Net ties are mythical and only appear fleetingly once in the v7 documentation - also for v8.
In March 2019 in the forum @eelik said
“In the future another kind of net tie is in plans. Until then you have to be careful when you use net ties.”
https://forum.kicad.info/t/net-tie-possible-bug-kicad-v5-0-2-1/15488
There are 3 other mentions of them in the forum, none with any helpful information.
So I still seek a method of splitting the GND and 3v3 Nets so that some have fine tracks, and some have wide tracks for lots of current.
And hopefully somehow splitting them will magically remove those wide clearance ovals around the MSOP pads.
Otherwise I have to start again from scratch and keep an eye on the MSOP each time I add a track. The board is large (675mm long, 50mm high) with lots of mechanically placed parts and up to 10 amp current. It is challenging to draw a track along that length because there is only a small window onto the board on screen, as well as then having to move the viewport to the MSOP each time for checking.
One way to get around it is to not use net classes. I have peeked at netclasses, thought I might use them for data pairs or something, but never bother to set any up. I have designed many boards quite happily just selecting the track size and via size as I route, and I can change track sizes willy-nilly (I often change sizes as I route a power tree around). I use whatever makes sense for the area of the board I am in – generally I have global board clearance set to 0.2mm, and I define track and via sizes I like. For digital stuff I usually use 0.2 tracks with 0.6/0.3 vias, analog areas usually 0.25 tracks since there’s more space, power tracks terminating at chip pads and caps are 0.3mm and short, transitioning to 0.5 and up to perhaps 1.5mm as they go further down the power tree. For power vias I generally use 1.0/0.5, 1.3/0.8 or larger. I only use a net-tie for connecting analog/digital ground, connecting signal ground to an esd ring, or other specific use cases, not in the power distribution. Just my way of doing it.
The willy-nilly approach is what I use, but it seems to be part of the problem. The original question is that I can’t route tracks on to the MSOP because at some stage, the perfectly good footprint has acquired clearance ovals on the pads which prevent tracks being made. How can I change those clearance ovals? I subsequently explicitly defined narrow tracks and small clearances for the respective nets but it has no effect.
File > Board Setup > Design Rules > Constraints > Copper > Minimum clearance.
You posted an image of the page, in this thread, earlier. The image shows .2mm setting.
Functionally a net tie is similar to a zero ohm resistor. It can be used to split one net to two different parts (or more, forming a star connection point). In KiCad it is implemented as a footprint which ties two (or more) pads together with copper, so that the result is like zero ohm resistor/resistors without a physical component.
The current KiCad implementation is more advanced than what it was back then. You can open one of the NetTie footprints and see how it’s done. The important part is in the footprint properties:
Now I see the “pattern”. thing. A pattern is a text string that is used to assign a net to a netclass.Such a pattern can also contain wildcards, so you can put a lot of nets into a netclass with a single pattern.
For your clearance problem around the pads you will have to change the clearance. At the moment just the clearance around a pad overlaps with the copper of another pad. This will always generate DRC violations.
Your MCP0808_MSOP symbol has (by default) the footprint: Package_SO:MSOP-8_3x3mm_P0.65mm assigned to it. This footprint has a pin pitch of 0.65mm, 0.4mm wide tracks, and that leaves only 0.25mm of clearance between the pads. This is not extreme, but this package is small enough that you have to be a bit careful with how you connect tracks to it.
Now you are trying to do at least 3 different things at once.You are fighting with the clearance for this footprint, and you are struggling with track widths and how to change them, and your perception of net classes and how they work is probably also not clear. Try to tackle one problem at a time.
I suggest you start with netclasses. Make a few net classes, put some tracks in each netclass, change netclass settings for track width and clearance and then see how this behaves. After that, learn how to change track widths without changing the netclass settings of that track. Put some widths in the pre-defined sizes list, and change the widths of some of the tracks. This is also a good moment to experiment with the toggle switch to use track width of an existing track that I showed earlier.
If you have done these two things, then you have enough knowledge to fix the clearance problem with your footprint. You probably also want to experiment with: PCB Editor / Preferences / Preferences / PCB Editor / Display Options / Clearance Outlines This has a selection list and a checkbox to tell KiCad when to show the clearance outlines.
This is my original schematic for the MSOP MCP9808 thermometer, which has the overlapping clearance problem.
I have edited the schematic so that all local tracks are independent by removing the 2 embedded SDA and SCL entries, and making the main 3v3 and GND connection, as well as the Alert connection, all connect to a new net called THM. The whole chip should now have none of the previous nets connected to it.
Then I updated the layout from the schematic, and for good measure I updated the thermometer footprint from the library (which obviously said no change, so no effect).
I went into to Board Setup > Design Rules > Net Classes > Netclass Assignments and set this new net THM to my Fine track with 0.2mm track and 0.2mm clearance.
I still have the clearance problem.
There seems no good reason why the clearance ovals are so large.
(I previously managed to get the top right pin 8 working using a similar trick of isolating it).
@paulvdh I totally agree about the need to focus on one thing. I have previously set individual track widths by simply double clicking on them and changing the width. I think I do know what a net is, and how to set net class values as I showed by setting the special net THM and assigning it my Fine track.
But I can’t find what is causing the clearance ovals to be the size they are. My Minimum clearance is 0.2mm and so is my Minimum track width.
It’s nice to see net names on the pads, but shorting Power and GND on this IC is not a good thing.
Note that pin 7 of your footprint now does have a narrower clearance that fits in between the pads. Creating a netclass is not enough, you also have to assign nets to your netclass. From your previous screenshots, I see you have already created a bunch of net classes (why so many?) and assigned nets to them (with the “patterns”).
Now your next task is to figure out why pad No 7 with the net Net-(U2-A0) has that smaller clearance. Your Fine netclass appears to be the only one with a 0.2mm clearance.
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Hmm, if it was me I would save the project with a new name for testing, delete all net-classes and see what happens.
I have removed a lot of this project, and what remains still has the problem of the clearance ovals. I attach a zip of the reduced project. This is purely to demonstrate the problem. The schematic around the MSOP thermometer has been changed to remove any extraneous connections, which is why 3v3 and GND are on the same THM net.
Main-Boardv2.0_test.zip (398.1 KB)
I still have the problem in my much larger project, and I am seeking help to resolve the problem there.
You have a very long list of names in the “pattern” column:
It’s good that I now see only two netclasses (Default and Fine). That avoids some causes of confusion.
There are a few weird things about your table though. First, any net that is not in this table will have the Default netclass, so you don’t have to put those at all in the table.
I also see a lot of /IO* net names listed. Those can all be contracted to a single table entry by using the wildcard as I did. However, these labels are not even in your schematic, so I don’t know why they are in the Netclass pattern table.
And for your immediate problem, the net names do not match, you have to put a slash in front of the THM name. Like this:
May I suggest to you to read this part of the documentation:
@paulvdh that finally resolves my problem. The Default Netclass was being applied and is too large.
I have now read the documentation and learned more about it. I think my project used an up-cycled previous project from a few years ago, because I certainly hadn’t set the Default Netclass.
The default netclass is always present in each project. That is why it’s the default
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