As I’m doing the simulation, I noted that, the “Do no Population” is very nice, because it visibly show on the schematic bay gray out. But when toggle a lot of “Exclude from Simulation” and they are not visibly on the schematic made it very confuse, and lot track of what been excluded? Are the a why I can configure KiCad 8.0 to have the similar behavior of “Do no Population”?
Doing both a simulation and PCB creation from the same project / schematic is fine if it fits reasonably well. However, when projects become more complex, dealing with the differences for the simulation and the PCB becomes a bore. At some point you are better of in making a copy from the project and then use one project for the simulation, and the other for the PCB.
When doing this it’s still an advantage to do it all in KiCad. Partly because you don’t have to learn a new user interface (LTSpice has always been atrocious in this regard) and partially because you can simply cut & paste to copy parts of your circuit between those projects, so there is no need to re-enter the schematic at all.
I agree with your statement, but I my question isn’t about intend of have a full PCB design and full simulation. It about just how do simulation easier around the visibility distinguishable between that “exclude from simulation” been tick on/off on the schematic.
As far as I know, the Exclude from Simulation attribute is mainly intended for parts that never have to be in the simulation such as connectors, mounting holes, logos and such.
As far as I know there is no way to make this attribute visible on the schematic.
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