How do I go about doing something like this? I have a few subsheets made, with transistor circuits to act as logic gates. I want to use Eschema to simulate these logic gates, but have no idea how to do so. Can I do this, and how?
Here is where I found the circuit designs, great channel:
I created some simulation examples of logic gates using mosfets, the principles should be similar.
Alright! Any way I could help add gates?
Is your goal to make gates out of BJTs because that seems like the most straightforward path to simulate the gates you need? Or do you actually need to simulate gates built specifically out of RTL (resistor-transistor-logic)?
I don’t care at this point. BJTs(whatever they are) sound like a good idea. Eventually I want to make a physical logic gate kit, but That does not relate right now. How would I get into BJTs?
OK, that’s what I thought. You just want to simulate gates no matter what they’re made out of. BJTs are bipolar junction transistors which is what your video up there is using for its RTL gates. Anyway, since you don’t care about that, I would suggest @holger 's link but then scroll down a bit further to the digital section There you can find some SPICE libraries that simulate 74HC-series gates.
I read the link on my phone, I also caught the digital section. will be trying it out as soon as I can.
1.) Right-click -> Save Link as…
2.) I think you’re misinterpreting it. Not your fault since it’s kinda confusing how it’s written. He says pure digital simulation is not possible, but then provides a way to do an analog->digital->analog method using libraries he created. Follow the instructions and give it a shot.
ADMS is related to this, but probably far more than OP wants / needs:
Ngspice and ADMS for Verilog-AMS modeling
ADMS is a code generator that converts electrical models written in Verilog-AMS into C code conforming to the API of spice simulators. The generated code will then be compiled into the simulator executable and the new device is ready for simulation.
What is Verilog-AMS ?
Verilog-AMS (AMS stands for Analog and Mixed Signals) is a language designed to describe and simulate analog and mixed signal designs using both the top-level design methodology as well as the more traditional bottom up approach.
ADMS uses extensions to the Verilog-AMS language, developed for compact modeling of devices.
Adms is used to translate analog transistor models from Verilog A language to ngspice C code. There is a special flag for compiling ngspice with adms (see manual chapt. 32). Then one gets access to Hicum, Mextram bipolar models and PSP MOS models, all dedicated to integrated circuit simulation.
The user cannot apply adms for reading arbitrary Verilog models. Extending ngspice here would be a very nice work for an very experienced C and Verilog programmer.
A post was split to a new topic: Generate Verilog from KiCad schematic because this is a 4-year old thread and an announcement deserves a new thread
This thread is 4 years old. Better to start a new thread if there is a need to discuss more.