thanks. If I’m understanding this correctly, the net-tie is an actual schematic symbol with an associated physical footprint on the pcb? It’s not just a logical construct, but actually takes space on the board layout. The “real ties” in V6 will presumably solve this problem with a purely abstract tie?
OK, so where does the “NetTie” symbol live? I have one in my personal symbol library, but I can’t find it in the default KiCAD library of schematic symbols. (The footprints have their own folder, “NetTie.pretty”, but I can’t find the default schematic symbols those footprints are assigned to.)
Real net ties also take space on the board. You can decide how much space but there needs to be a physical location where (x,y) = Net1 and (x+1,y) = Net2. So, at a minimum, the net tie needs 1 unit on the board. Realistically, your two nets need at least 1 track width separation.
I don’t know the internals of eeschema or pcbnew, but I would think that conceptually one could allow two networks to meet at a pin/pad and require no other physical artifact on the board. It does create a problem in that currently a pin is associated with a single network.
Sure. That’s allowed right now. That is, in fact, how net-ties are implemented. You have a pad that has one net connecting to one side and a second net connecting to the other side. You require no other physical artifact.
I think what you are describing is one network with two names. Just because the traces are a different width doesn’t make them a different network electrically. The current software can only handle one name per network.
This is an organizational tool you have decided to use. This is not wrong. That is why there are net ties. They help the designer maintain their logic and lets the software maintain its logic. Otherwise you would have to do something like place a jumper or zero ohm resistor.
From the standpoint of circuit theory, they ARE the same network. But they are different when you make a physical implementation on a PCB layout, because the two segments of the network have different geometrical constraints (minimum width and/or spacing). I’d like to have DRC recognize the differences, and evaluate each segment according to its own constraints.
Seems like some kind of alias problem for the software to sort out in the long run. Seems that would be simpler in the schematic portion. Maybe the PCB portion wouldn’t be too bad if you could define exceptions to the alias to allow interconnecting.
The problem is you still need some check to make sure it is what the designer intended. If they have to put in a net tie, problem solved?
The schematic is a mental abstraction. The board, on the other hand, is a physical entity, and a physical item - such as a net tie - is the most user-friendly way to mark the point where two nets separate. It’s a location you can park a cursor over (or point to, or stick a 'scope probe onto) and declare with certainty,
On this side of the net tie, this electrical connection is known by a particular Net Name. It has certain properties and constraints. But . . . . on the other side of the net tie, it is called by a different Name. Its properties and constraints may also be different.
I have no problem with a Net Tie being physically represented as circle or square of copper, with dimensions equal to the track width. That way it can be easily selected in PCBNew, its properties examined or edited, and its location changed if necessary. I believe this approach is superior to reducing the Net Tie to a purely logical concept, with physical dimension sizes of zero.
I have no problem with a Net Tie being physically represented as circle or square of copper, with dimensions equal to the track width.
After reading all this I understand the need (or at least value) of an explicit schematic symbol to indicate intent when joining two nets. LIkewise, having some physical representation in the pcb view serves to control where on the board the junction between the two nets occurs. Is there any way to have a footprint that sizes itself to the trace width? Otherwise we end up needing a footprint for each trace width. Furthermore, should we change the trace width, we would have to replace the footprint with one that matched. I suppose it would probably work to have a footprint that’s some min trace width, since the trace will overlay it in most cases.
The typical use case for net ties is when you want to ensure that the connection between two nets occurs at one controlled location . A good example is a ground star point a shield/ground connection or power supply connection.
Net aliases on the other hand , as you have it now , is a way to use different net names in schematic so you can use the most verbose name in a given context, but have ratsnest on the PCB, in this case pcbnew applies net precedence rules to determine what the net name is in PCB .
One use case for net aliases is when connecting up an MCU with many pins, it is convenient to be able to refer to a net by the MCU pin number as well as configured/platform function and perhaps by it’s hierarchical name as well
I’d like to have a possibility to specify (for DRC) that main(long) VCC line is no thinner then for example 40mils, but at the same time if I have some 100k resistor connected to VCC then DRC would have no problem if I made this connection with 10mils because had to go under other 0603 element. And adding net connectors for all elements connected to VCC because of this seems not the simplest way.
I’ve got an idea. Would it be difficult if I could use two colours for wires at schematic (I think red=main, blue=side connection), and specify two rules set for PCB. At first moment seems simple, but as PCB can be organised completelly different then schematic it would be hard (and sometimes impossible) for software to decide which track is red and which blue.
So the other idea. For each net you mark two pads connected to that net. DRC would have a task to check if connection betwean these pads is wide enough (extra parameter for that net).
I am just loudly thinking. Don’t know if it can be practical or usefull.
From the standpoint of circuit theory, they ARE the same network.
The problem is “circuit,” i.e. lumped elements. In reality, lumped elements are idealizations of real-world components: a capacitor stores only electric energy and an inductor stores only magnetic energy. In reality, one is a little bit of the other and as frequency increases (wavelength decreases), so circuit/component dimensions become a significant fraction of wavelength, the real nature of components becomes apparent. So, instead of designing with separate inductors and capacitors, you design with cavities, which store electric and magnetic energies simultaneously, i.e. distributed elements. Similarly, as frequency increases, traces are no longer “wires” (lines in a circuit diagram—a lumped-element concept). In fact, you can design actual filters from circuit traces (which are a significant fraction of wavelength).
The problem is that the layout DRC “thinks DC” (in terms of lumped elements and wires in a circuit diagram, as you describe) instead of thinking “RF/μwave,” where the dimensions of traces are a significant part of a wavelength. To be sure, this problem is not peculiar to KiCAD only. I have encountered this problem with well-known industry standard packages (and layout people who cannot understand these concepts). Take the PIFA (Planar Inverted F Antenna) as an example (see the link below). There are three ports available to this structure (the tip of each arm of the F and the base of the F), which all look connected @DC. However, one of those ports is the feed (“hot”) and at least another port is grounded. To the DC-thinking DRC, that looks like a short; however, it makes perfect sense at RF because the trace is designed to be a significant fraction of wavelength.
BTW, Digital design can be just as demanding. In RF design, you usually have a carrier which is modulated so that the bandwidth of the imposed modulation is a small fraction of the carrier’s frequency. In digital design, there is no carrier. In digital design it is the edge rate which determines the range frequencies to be supported, not the clock frequency. You can have one pulse per year, but if its rise/fall time is 1ps, then you probably need high-speed design techniques. Different losses of the PCB dielectric and metal traces at different frequencies (i.e. dispersion) may cause unacceptable pulse-shape distortion.