OK, I have managed to reproduce this in a nice small schematic using only standard library items. It is related to the busing. It’s definitely a behaviour change between 5 and 6 and I’d consider it a bug.
VersionTest.zip (3.8 KB)
Note the highlighted net is composed of nets that remain separate in version 5. They are shorted on reading into version 6. I suspect the problem is that version 6 is interpreting the sub buses that are dropped off of the main bus as if they are the full bus. This is contrary to version 5 which correctly interprets them as subsets. It’s also, in my opinion, contrary to the principle of least astonishment. I would have expected it to work as it does in version 5.
The example I’ve done showing the issue sort of illustrates why it’s useful to behave in that fashion, but you can hopefully see why it’s useful for fanning out or merging signal buses. An example might be merging analog input signals to a central, high channel count converter, where each input channel requires significant conditioning and power management.
I think this likely accounts for most of the remaining issues since this particular schematic has multiple such buses with subset branches.
BTW, the zip is the original Rev 5.