I can’t think of anything other than the following solution, which I find somewhat cumbersome.
I would find it very useful to have some option similar to, for example, assignment in VHDL, which allows you to slice a signal and connect it to another bus.
the splitter in VHDL is more or less the same as your splitter module in kicad. the only difference being the one is text-based, the other one graphical.
I think there could be a walk around with using the bus definitions but I am not to fimiliar with these to be able to help here.
If you don’t have to rename your bus member signals branching obviously will get easier.
This is not possible in KiCad today but it’s an interesting feature request. If you file it on GitLab we can think about various ways to implement it.
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