Boundary around a footprint

[Robin_Gangopadhya]

pl, SEE SCEENSHOT: why do we see a boundary around a footprint of a test pin or single PTH used as a pin?
When it is a hindrance, how does one remove it? For example in case of a copper area that you want to include this pin or Test Point?
-Any help will be highly appreciatedfootprint_boundaries.pptx (191.7 KB) .
robin

[HiGreg]

Try to include a graphic image instead of a powerpoint file. PowerPoint is not a safe or super common format to view from an unknown source.

[Naib]

for convenience

This is CLEARANCE and can be found under Board setup -> Net Classes.

This shouldn’t be removed but set to an appropriate value in accordance to your prefered fabricator’s capabilities.

A good example is jlcpcb
https://jlcpcb.com/capabilities/Capabilities. If you remove this CLEARANCE, you will be able to track traces at a distance that might not be manufacturable

[hmk]

If I understand you correctly, you want to connect the PTH / pin to a copper area?
In that case, the PTH must belong to the same net as the copper area (unless you use a workaround that will break the design rule check).

[Rene_Poschl]

The pin needs to be on the same net not just the same net-class (a net-class is a collection of nets for the purpose of giving multiple nets the same DRC rules like clearance, width, via size, …)

[Robin_Gangopadhya]

Oops- I should have remembered this - apologies.thnx

[Robin_Gangopadhya]

thnx Rene.
I think this shows up only when the footprint is a single entity. It has always been this way- and we almost got boards done with no inner layer copper land connected to single item ftprnt such as Test Point or Milmax pins All nets in our practice have names and naturally nets of same name connect. A via will . Pad of a part will. But not when ftprnt is single item.

[hmk]

Corrected, stupid typo / mistake from my side…