And you are sure he understood it well?
Your sentence:
Can be understood that if other tracks make GND fill to have several not connected islands than using a short track on the opposite side you can connect that islands together. This has not a lot with ensuring the return signal path just along the signal track.
That’s your interpretation. Simply set “Remove islands: Always” (the default).
And that’s your interpretation. I was speaking about islands that are connected to at least one GND pin so not removed by this setting.
I’m not sure to understand that concept, it’s kind of advanced and I’m just beginning. I’ll try to read more about that. But anyway, I need to use the back layer to put some traces, otherwise it’s impossible to route all my traces. I’ll try to reduce it to the very minimum.
My pcb looks like this:
front layer:
Do you think that it will cause real problems to have those traces on the bottom ?
You didn’t considered using 0Rs to jump with one track over others 
(with 1206 0R you can jump over 4 or 5 tracks).
First approach is just to use both sides for tracks (no zone fills). We did our PCBs that way in 90s until we had a problem with device that hang-up each spring and autumn during storms. It happened only at one of our 100 installations all over the country. It was in the highest place locally and many lightning strikes there. PCB design was not the main source of problems but collecting all information I learned (by the way) that PCB should be better designed.
Second approach is to use zone fills the way you have at your PCB.
Third approach is to limit openings in GND zone to very small ones. To just cross tracks you need only short track section. In most cases it is no problem for electrons if track has a complicated shape just to make such solution possible.
Fourth approach is to replace such crosses with 0Rs.
I think third approach improves a lot PCB EMC properties over second approach.
Fourth gives even more but there is no big difference between third and fourth.
I typically don’t need a lot of 0Rs because to limit VCC current pulses at most digital wires I use small resistors (like 100 ohm). If digital output switches the IC needs a current pulse to reload connected to that output tracks (if you have GND fill track capacitance is bigger) and other ICs inputs. The faster switching the higher current pulse needed. Thanks to such resistor only the own output capacitance have to be reloaded at once and rest slower (100 ohm * 10pF = 1ns - not important in most cases). This reduces spikes a lot. This resistors helps me also to not need to use second side for routing.
Limiting current pulses is also good for PCB EMC properties.
I use fourth approach since I was solving that problem with storms. Later we (Poland) joined EU and EMC tests suddenly became mandatory. When I went to lab to test our devices they were surprised that each one passes all tests with no problems.
I didn’t look at this carefully, just a general remark: you should stitch the front and back GND layers together with vias. Especially every sharp corner of a fill and then other corners and near all fill edges. It doesn’t hurt to have more than enough, there’s room for hundreds of vias. Like this. An arrow points to a place when you can move a track a little bit to fill more of the empty space.
All these vias give continuity for the GND copper. Otherwise you loose the benefit of copper pours because the current must find its way through longs paths. (EDIT: this depends on the frequency of the signals; see posts above which I read only afterwards. DC likes to find the shortest route. In any case it’s good to connect the front and back layer fills.) Without vias you also will have potential antennas, like here:
You can remove narrow antennas by moving some tracks closer together. In this case moving the front track above the GND slit (pad 4) downwards could even give room for more useful stitching vias.
Oh thanks, I never thought about that. It’s good to know. I’m trying to follow your recommendations the best I can, I tried to move from second approach to third one (easier compared to fourth one).
I reduced the track the the minimum I was able to. It looks like this now:
)
It’s really interesting to see the approach with 0R, I was not aware. I’ll give a try with that in my next pcb design for sure. This one is my very first design so having a pcb that is working and doing what it should would already be a first victory for me 
)
This is also a very interesting information. I tried to clean up a bit the back side until now, and I’ll tackle that right after. If I understand well, the more via I have the better, is that statement correct? I think I got the idea of having via at all possible places where a current could wants to go to make path as straightforward as possible. Thank you for pointing that out
Disclaimer: I really know nearly nothing about electronics (hyperbolically speaking, for the sake of making sure you know you should consult some more knowledgeable source).
Within limits of common sense. Don’t add as many vias as you could with the manufacturer’s hole to hole clearance.
Vias make the GND copper as continuous as possible. You could think it this way: one purpose of the plane is to make sure any two points belonging to the ground (or some other plane) have as small difference in potential as possible. The longer the shortest path between two points, the worse. Adding vias shortens the route.
When there are high frequency voltages/currents/electromagnetic fields things go complex. In GHz range it turns into black magic. Sharp corners or long protrusions can act as receiving or transmitting antennas. Copper areas which may work as antennas can be removed by adding vias connecting to the copper fill on the other side of the board.
Jitter | Electronic Design and Consultancy (a plus for nice screenshot illustration clearly made with… guess what)
Ground Plane PCB: A Return Path for Circuit Current and Components
Understanding 2-Layer PCB Ground Planes | PCB Design Blog | Altium
Thank you for your answer. If you “know nearly nothing about electronics”, I probably know nothing The concept of return current loop seems to be a bit difficult to understand
as I’m just beginning as I’m lacking some basic knowledge… I’ll read more and try to understand but for now I will try to do something simple to start with.
What do you think about this:
Do you see big mistakes ?
Just have in mind that current always flows in a closed circuit. For each current flowing from your source to destination the loop have to be closed someway. You have a control of way it takes from one IC output to other IC input by routing track. But you have less control of the way back. The smaller the surface surrounded by this circle the better. High frequency current helps you to minimize that circuit as return current prefers to return just under the track so the PCB thickness is what decides of circuit area (look at PCB from all sides as electromagnetic fields don’t follow our way of looking at PCB in editor).
If you have 4 layer PCB with GND and VCC zones at inside layers than whenever fast signal track jumps from top to bottom then near that via you should have a capacitor connecting VCC with GND as return current travels through the nearest to track zone and at that point it have to jump from one zone to the other. If it have to find the long way then the area we try to minimize is increasing.
If you want to be good in PCB design read the articles I have mentioned previously.
It is much, much better than previous.
I don’t know your circuit. If it is purely low frequency than it can be not very important, but I simply prefer to do everything the best I can.
If it were my design I would not accept the big openings in GND zone for a series of pads. Clearance have to be smaller or pads have to be smaller (or oval). The task is to allow zone to pour between all the pads (I typically use 0.25mm zone clearance).
Make fills at top to function as part of bottom zone. They should be connected along their all borders (add some vias along PCB border) and I would also add randomly some vias inside bigger fills at top. I don’t have other arguments for it beyond that I just feel it is better.
thank you for the explainations about the return current loop , It helped me a bit, still not 100% clear but I’ll continue to read articles about that. It seems to be an important topic, I’ll try to understand that !
Good Thank you
Really interesting remark, I did not think about that ! I’m now trying to improve that point. (Don’t hesitate if you have other points that I missed like that one, your precious remarks are very appreciated)
I lead me to one more question , what do you think is “reasonable” in term of clearance for a pad ? Because I don’t really know what is acceptable, I suppose I can not put a clearance of just 0.2mm for all pads. Isn’t it a bit risky to have ground zone that close to pads even (magnetic field can maybe cause unattended alternation in signal?). Do you have an opinions on that ?
I was already able to improve a bit TH pads from the central footprint (by changing zone clearance and pad dimensions). It looks like this:
But for the TH pads on the left I don’t understand from where to clearance is coming from. I checked all the settings I know and it seems to still be bigger.
Example with TX1:
pad
We can a clearance of 0.4mm and I don’t find where this come from
Design rule constraits:
There is not pad clearance on the pad itself
TX1 is using the netclass “Signal”. The netclass is configured to have 0.2mm of track clearance (There is no option to configure clearance onfy for pads as far as I know)
The zone is configured with 0.254mm of clearance
I have the impression that there is one 0.2mm clearance around the pad coming from the netlist (marked with the yellow border) but where is coming from the other 0.2mm of clearance is a mistery to me ^^ I can edit pad properties of all pads to put a “pad clearance” as I want, that is working fine, but it seems to be a bit hacky and it’s probably not the right way of doing it.
In all cases it is a really good advice that you gave me. It seems way better now . I just need to figure out what is an acceptable clearance between pads and groud zone (thinking about 0.2mm, but it’s maybe not enough).
Current result:
Many thanks for the time you are spending on helping me You saved me from lots of problems that would be discovered too late (after having ordered the pcb) I now understanding the importance of having a good ground zone ^^
I assume the GND zone has the “Power” netclass, which has a general clearance of 0.4mm.
Out of curiosity, I checked my current PCB that uses a lot of zones. Nowhere can I set the power netclass. Still they are GNDA, GNDD, 5VD, … with a PWR_FLAG in the schematics. And the clearance is 0.2 mm as in the zone properties and verified with the ruler.
To the OP, it looks to me, as if the clearanc is the same for your zone (look at the vias). This should not be the solution, but maybe you try to set the termal relief gap to 0.254 mm.
Yes the GND is using Power netclass but I don’t think it is the problem as in the example I’m taking TX1 that is using Signal netclass.
I already tried and it does not change anything. There is a clearance of 0.4mm around pads using “Signal” netclass. I really don’t get from where the extra 0.2mm comes.
If GND takes 0.4mm clearance from Power netclass settings that means GND net to any other net have to have clearance 0.4mm. So when you have GND zone it have the clearance of 0.4mm to anything else.
But GND pad to GND zone have not clearance from Power netclass. Clearance don’t works from net to the same net.
With GND pad the 'Thermal relief gap works that happened to be also 0.4mm.
So that way you made all pads to have 0.4mm distance from GND zone.
Reasonable clearance depends on voltage difference between nets. If you don’t have higher then 12V voltages at your PCB then there should be no problem to have 0.2mm clearance.
For reasons of historical habits I use 0.2mm clearance for Default net class and 0.25mm for zones. In past where PCB factories had no electrical check of manufactured PCBs it happened sometimes shorts between nets and the long distances of different nets being close one to another is between zones and other tracks. So to reduce the risk a bit I used (and still use) bigger clearance for zones.
For me VCC and GND also belongs to Default netclass. I just manually select track width when routing.
I add the second netclass when I have nets with higher voltages (like 24V or PoE 48V) just to specify clearance 0.4mm.
Look at your picture pad 16 +5V. Track protrudes beyond the pad. In such case I am trying to have last, very short segment (whole inside pad) with lower width to not have that effect. KiCad doesn’t help in it. In fact, it does everything against such a solution. When you go inside pad it jumps to its center. Zooming in doesn’t help. When the pad occupies the entire screen your cursor will jump half the screen realizing the snap to pad function.
I have reported 4 or 5 years ago that snapping should be limited to some distance in screen pixels but it looks that it is only my problem.
Switching on and off snapping is not the good way as I want that short track inside pad to snap to pad center (helps in case of dragging a footprint).
As an exercise find the way how to do it
Since I use KiCad (2017) I have to do it with almost all pads at power tracks as tracks are wider than my SMD pads they are ended at.
Then that is the problem. Clearance is typically computed between two different nets, in this case between GND and TX1. The larger value wins.
It make sense, I don’t know how I missed something that big ^^ I now understand your previous answer Thank you for clarifying that
Yes I totally missed that point. It was obvious thought ^^ Now it’ s clear, thank you for that very clear explanation
The maximum voltage that I will have on that pcb is 5V. I’ll follow your recommendation and set 0.2mm for the power netclass. That’s answering my 2 questions (0. 4mm clearance + acceptable clearance). Again your answer helped a lot
And that’s cool, I was pretty sure that there was a feature in kicad for that, I searched for more than half an hour yesterday ^^
I think I found a way, I just created a track the same width as the pad and placed if from left to right. I just had to ignore the warning that the track is not connected. Is it how you do it as well ?
(the pad is hidden on the image to make the track visible)
