Are sharp corners still a bad thing

While routing, I get some sharp corners, angle less than 90 degrees, in past they were not so good because acid could stay during PCB manufacturing. By the way, a beginner with Kicad like me, find it hard to clean up those tracks.

Fine detail or sharp angles are not an issue for commercial PCB mfg.

However I would suggest you do not use the default trace size and via size. They are set to what most manufacturer’s minimum allowable. There is no need to use these minimums unless the routing becomes very congested and must be used to make connections.

I suggest you increase both by 50% or even double them.


I’ll check what the rules are in this project (I didn’t start this project).
Thank you for information

The V5.1.x default track and via are very coarse by modern fab standards.
I often go finer on both with low cost fabs (but not to the limits), but if I don’t need to I leave them alone


In the screenshot there’s for example a track (red) to the rest of the +3.3v from a via. It should be very easy to clean up by hovering over the short track segment, clicking D and dragging a bit upwards/left. The same is true for those pad/track corners: drag a bit to some direction and a new corner is created and dragged, the track leaves from the pad with 90 degrees.

1 Like

I use 0.25mm (10 mils) tracks whenever possible. Where not possible I use 0.2mm tracks.
I specify minimum clearance 0.2mm but when routing I try to left always a little more space than clearance lines show.


My standard too.
I also add a 0.6/0.3 mm via, smaller than the standard 0.8/0.4. This makes a huge difference on 4 layer boards with 0.4 mm pitch pqfps


Good advises. It is somehow difficult to remember good values when environment or CAD is new.

I usually try to avoid minimum clearances and widths.

Leif M

I mainly use 1.0/0.5mm vias, but because of 2 layer and bottom whole GND I have only GND vias.
If no space I use 0.9/0.4. For via-stitching GND zones at F and B I use 1.2/0.7.
In thermal pads I use 0.3mm or 0.25mm holes.

0.3 mm is much better in thermal pads than 0.4 mm, it makes solder theft tolerable, without going to the cost of filling.
I don’t go as far as 0.25 mm as that would limit my fab choice too much.


I will second this but also say I default to 0.25mm/0.5mm on 4-layer and higher boards (I haven’t seen a fab where this is an issue yet)

I did it recently (few months ago) because I have read (probably at this forum) someone saying that he sow 0.3mm holes thefting solder. Our (very small) contract manufacturer had something against going below 0.3 but not listening him I did it.

My experience might be a little on the old side, however although processes have changed physics have not.
My viewpoint comes from experience with PCB failures during life testing and fortunately very few customer returns.

Summary: Although PCB can be mfg and assembled with very small via’s, my experience has been they should be avoided if at all possible. I don’t know the ratio of hobby boards to production boards from the posters in this forum so I’ll direct my comments to the hobbyists and believing the production folks know what they are doing.

Hobby boards often have a tough life. Trace cuts, jumpers, over currents etc. The “minimum” capabilities of the mfg are valid, however the robustness of the design suffers if the minimums are used without understanding the implications.
My suggestion is to increase the minimum trace widths and via holes. At least until you get to a situation that absolutely requires them.

Below is a cross section of some via I found on the internet. Its been years since I had to have a board sectioned and only recall the results by memory.

Below that is an analysis of the copper in a 0.3mm via hole.

After the drilling process is complete, a thin coating of copper is chemically deposited on all the exposed surfaces of the panel, including the hole walls, using an electroless plating process. This process is required to deposit a thin conductive coating of copper to the fiberglass of the hole wall so that the holes can be subsequently electroplated. The thickness of the electroless deposit is typically between 45 and 60 millionths of an inch.

1 oz copper (~35µm thick or 1.4 mils)

So 60 millionths of copper = 0.060 mils

therefore: the thickness of the copper in a via compared to a copper traces is ~ 0.060 / 1.4 = 4.2%

Now a 0.3mm via hole is approx. equal to a copper trace of:

Circumference = πD = 0.3mm * 3.14 = 0.924 mm ~ 0.04 "

compensating for the thickness of copper… **the equivalent copper trace is approximately equal to a trace width of 0.04" * 4% = 0.00016" (or 0.004 mm)

Jumping off of @JohnRob’s point here, specifically for boards that are expected to be modified (early prototypes, hobby boards, etc), when choosing via drill sizes, try to choose a hole size to fit your normal bodge wire. In a past job I usually used 30AWG wire-wrap wire for my bodge wires so I would make sure that vias would fit a 0.01" diameter wire with solder. (I’ve since forgotten the size I used.) I would also avoid tenting vias. This often provided a convenient place to re-route a connection with a bodge wire cutting down the number of places I would need to scrape mask from a track to solder a wire. No, it didn’t always avoid having to scrape resist from a track, but it often did. YMMV

1 Like

I find your post both confusing and/or misleading. (I think so).

First, nice picture of a PCB cross section, but I am not sure what sort of point you wanted to make by posting it. The via in that picture was perfectly all right before someone cut it in two. I had to stare a bit at the ends of the via, but it’s just some solder mask being partially sucked into it but if you look at the walls, then you see the copper plating all the way through from bottom to top.
It does show that the holes can get closed at both ends, and this apparently may lead to production problems if there is liquid trapped which may evaporate violently (explode) during soldering.

I got lost in your calculations where you jump over the atlantic ocean a few times like it’s nothing.

Normal PCB process starts with copper of about 17um, then via holes are drilled and covered with a very thin conductive coating, and then the via’s are plated and the copper thickend to approx 35um. The via’s will receive about the same copper thickness , so 35-17= 18um.

I can follow you through:

I’d like to add that copper thickness of a via typically is about half that of the copper tracks, so you’d need twice the circumference, so a 0.3mm via is approx equivalent to a 0.46mm wide copper track.

I like SemazuruCDE’s remark better.
Bigger via’s (and not tenting them) are good points both for soldering in bodge wires and as test points for an oscilloscope.

1 Like

What do people think about VIA collars or how much larger should VIA PAD be than the VIA hole.

Those are typically called “annular ring”, and it’s minimum size is dictated by the tolerances in the PCB manufacturing process. The goal is that the side of the hole does not touch the outside of the annular ring. Different PCB manufacturers have different tolerances here.
Typically the holes are drilled and plated before the copper is etched and the positioning of the big panel is never perfect, there is always some tolerance. Especially on multi layer PCB’s, the PCB can deform during pressing and curing of additional layers. Eurocircuits has made some nice Youtube video’s about PCB manufacturing.

I know nothing about it, but according to my imagination access of cooper to surfaces inside 0.3mm holes is probably much worse than access to PCB top and bottom surfaces.
I would be not sure if thickness inside vias is the same as increase in cooper thickness at PCB surfaces.
I remember times where it happened that vias got not contact sometimes. I suppose that current process guarantees contact. So I suppose thickness spread is not from 0 till 18 but may be from 9 till 18.

From what I’ve read (I’m no expert on PCB manufacturing) a main cause of problems with via plating is the initial coating to make the inside of the hole conductive. If it’s not conductive, then no plating at all will be added. If he hole is conductive, then the copper plating works normally. So a 50% difference in thickness seems unlikely. It either works or it does not. What the actual tolerances are would be a wild guess for me though.

This is why many PCB fabs have an aspect ratio (PTH diameter vs. board thickness) spec. Smaller holes on thicker boards will have issues supplying fresh solution (both pre-plating and electroplating) to the inside of the hole. They do agitate the chemical solutions to try to push fresh solution into holes, but there is only so much you can do to combat fluid dynamics…

In my limited experience, though, this aspect ratio spec is hidden in their minimum PTH hole spec. Good board houses will alert you if you accidentally violate the aspect ratio spec even if they can physically drill the hole. But if you notice that they have a larger minimum PTH spec vs. their minimum NPTH spec, this is likely to be a contributing factor.