Perhaps I got caught up in my thought process and not explained clearly. And the information I found to support my supposition was not researched well.
My point is IMHO small diameter via drill sized lead to thin (and potentially fragile) current conducting path through he via.
And hobbyists are not aware of the what I have found as a weak point in PCB’s with small via holes.
My mathematical goal was to compare the equivalent trace size for a via using geometry. Perhaps more clearly…
The equivalent width of trace that a 0.3 mm via drill would be:
Circumference of the via = πD = 3.14 X 0.3mm ≈ 1 mm
OSHPark via thickness is specified as 0.0254 mm thick.
1 OZ of copper = 0.0348 mm
By calculation the via wall is ≈ 1/2 of the copper thickness of the normal trace.
The 0.3mm via copper “length” (aka the circumference) is 1 mm And if the copper thickness is 1/2 that of copper a 0.3mm diameter via is approximately equivalent to a 0.5mm trace.
So I’m somewhat embarrassed my assertation is not supported by the calculations. I apparently grabbed an incorrect (or at least not understood) thickness of the via copper in my #13 post.
My belief that a small via can have reduced reliability stems from experience in the aerospace industry were we had some of every log of PBB’s professionally sectioned. It wasn’t unheard of to find a lot where the inner plating did not meet thickness requirement.
While I’m sure current processes are much more refined. Current density in the center of the plated through hole will be lower than at the surface so naturally I expect the center of the via to have reduced copper thickness.
It is still my contention that hobbyists who have not yet learned the increased risk and reduced robustness of thinner traces and small vias, should use thicker traces and vias.
Look at the a board that stated this thread. Plenty of room to use thicker traces and larger vias.
Unfortunately this post is too long for most beginners to get through and will probably not meet my goal. However when professionals like your self say " I use “…” all the time it sends a message to the new hobbyist /designer that thin clad is OK. Especially when higher currents are employed in the designs. You guys know where to use what, but the noob does not.
While most seem fixated on the size of your tracks and vias, eelik did point out that your layout, in particular your component placement, could be improved. The screenshot you posted shows a very small segment of your layout yet there are many issues with your routing. To answer your question, yes, sharp corners are still considered a “bad thing”. Not in terms of fabrication but signal integrity, EMI/EMC, and just as important, cosmetically. While this project may not suffer much in terms of signal integrity it’s best not to start bad habits. Sharp corners, both internal and external, can almost always be avoided and therefore should be. It would take very little effort to clean up the routing in your screenshot.
In your screenshot the 3.3V essentially bypasses the decoupling capacitor reducing it’s effectiveness. The 3.3V then exits the pad of the IC and presumably supplies power elsewhere, or perhaps it connects to the power supply, which would be even worse. It does not seem to be a very well designed power distribution network (PDN).
You might want to seek a review of your entire layout before you get too far along.
@1.21Gigawatts is exactly correct. However don’t let the new concepts scare you.
In your design (what we can see of it) C26 is a “bypass” capacitor for the U? device.
The goal of C26 is to stop fast transients (spikes) from reaching U? power input pins.
The faster the spike is, the more any a small length of trace will be detrimental to the effectiveness of C26
In your case you should move C26 closer to U? power input pins and the 3.3v feed should come in one side of the c26 pad and out the other, exactly as you have the ground.
Quite nice talks for those technical rationales.
I would raher say, ‘symetrical routing’ (for the tracks up to the pads) helps better current fields for better efficiency.
Not only for beauty… (but most of the time Nature and Physics conduct to beautiful results ).
).