I’m doing my first 4 layer board using kicad and having problems filling the +5V and GND layers (the two inner layers).
I placed all components, routed all signals, and fixed all DRC except those telling me +5V and Gnd wern’t connected.
I added a board outline and some mounting holes (not plated).
Now im trying to fill the +5V and GND planes. I can draw the outline of the filled zone on the GND layer and set the net to GND but when i hit “B” I get a brief pop-up that says something like “Building filled zones” and nothing happens. I get same result on +5V layer.
Same result if I try filling just a small area of the board (eg under a decoupling capacitor connected to both +5V and GND nets.
If I create a new blank project and import the Board Setup i can fill the GND and +5V planes even if there are no components or nets. So its not like I have a massive clearance set.
Is there any way to figure out why the zone wont fill ? I seem to be stuck.
I suppose you do have via’s on the PCB to connect to the GND and +5V layers?
There is also not much info in your post to determine the cause. Can you upload a simplified version of your project? Just the PCB outline with just enough components on it so the nets have something to connect to.
Also, using both a power and a GND plane is not the best practice, (at least for high-speed digital signals) It’s an old practice, and it’s easy, but having two GND layers and routing the power as tracks is often a better solution.
Not sure from the description, but as all components are PTH then under decoupling capacitor both net pads should be available at inner layers to connect zones to them.
I have no KiCad V7 here. Is it possible that you put PTH footprint at 2 layer PCB and then you change it into 4 layer and that footprint have no pads at inner layer?
If yes than may be updating from schematic can help.
I dont have vias connecting +5v and GND to their respective layers but I do have lots of PTH on components and the power connectors. The DRC checker tells me about 44 of each.
Yes I’m old school and the board is only low frequency. Mostly relay switching. Track density is very high hence using inner layers for power.
Its quite a big board so my plan after xmas is to make a copy and try removing sections to try and narrow down the problem.
Is there any reason why the PCB layer and the net on it cant have the same name? I renamed the inner layers GND and +5V.
No its never been 2 layer. Started out as a 4 layer.
I plan to try dropping a GND signal down onto that layer with a via and track just to confirm i can manually run GND traces on the GND layer then see if thatcallows filling to work.
I looked over the PTH part. With PTH footprints, they always reach the inner layers.
I doubt that would be a problem, but to remove any doubt, you can temporarily rename the layers again.
So, what is that error message?
The most common cause for zones not filling is a fault in the PCB outline. Does DRC give any warnings about the Edge.Cuts layer?
Another silly mistake would be if the net name of zone is not set correctly.
Don’t be too careful when doing this. Just make a copy of the project, and then delete half of the footprints / tracks of your PCB. If the fault still persists with a handful of footprints, you can zip up the PCB and upload it here.
I don’t actually get an error message when trying to fill a zone it just tells me its filling the zone but doesn’t actually do so. Problem occurs on +5V and GND layers.
Using different names for the zone doesn’t seem to make a difference.
Redrawing the board outline and/or the zone outline doesn’t seem to make any difference.
Deleting some or all components, all tracks or everything doesn’t seem to make a difference.
So I now have two simple Test projects (same schematic), one of which I can fill zones and the other I can’t. I can’t see any difference with board set up or the fill settings. Importing board set ups from working to a non-working design or vice versa doesn’t seem to change the status of either.
I believe the only difference is the source of the PCB files - the failing one originates from the project I’m working on (with all but two capacitors deleted). The working one I rebuilt from scratch.
I’m not sure if I have zipped these correctly. I just zipped the project folders.
I tried an awful lot of things today without success, but have eventually found a work around that didn’t involve redoing the PCB layout… In short I used File → Append Board to import it into a new file.
I created a new project and copied in the original schematic and renamed it accordingly.
I created a new PCB blank using kiCad defaults and changed it to have 4 layers with same names as the problem layout (eg +5V and GND).
I tested that I could create a small PCB outline in the corner of the sheet, put a zone in it and fill it. I could.
I then used file → Append Board to copy the problematic PCB layout into the new file. It imported with no errors (The rats nest displayed incorrectly but I ignored that).
I then checked I could add a filled zone on the Appended Board and I could (insert loud cheer).
I deleted the temporary small PCB outline and zone.
Then I ran Tools → Update PCB from schematic and the DRC checker. All seemed in order.
Then opened Board Setup and imported the design rules from the problem board layout (All of them).
Filled zones still worked.
Then I saved the PCB layout and saved the project with a more suitable name.
So my gut feeling is the problem was something to do with the original board set up but I couldn’t find any settings that were different between projects that had working zone fill and the one that didn’t.
I remembered that zones very easy are unfilled so supposed (I had no KiCad at hand) that it happens whenever you move footprint. Now I’ve checked that what I remembered was about any zone shape modification and not footprint movement.