Hi,
in another PCB program (circuit studio) when I was pouring a ground plane the plane didn’t cover wires,
and I kicked it to cover all wires and it made stray copper fingers.
I can’t find out how to fix it.
Hi and Welcome,
I don’t fully understand you question and not sure what “Kicked” is, do you mean ‘Kicad’ please ?
what it looks like to me is you have ‘copper islands’ or bits of copper that aren’t connected to any net. Is your copper pour attached to the GND net ? and what value do you have the clearance set to ? this tells the copper pour how close it can get to another area of copper (Pads and Tracks or other fill zones) Please post the Kicad version details as well 
I’m on version 7.0.2 and this is the setup for the zone.
my wish is that if I route a net from a part to a via the zone will not overlap it.
thankes for your help.
Looks like it is doing what it is supposed to do. Yes, the pour will cover traces if they are the same net as the zone (GND), and spread out like fingers until it hits the clearance you have defined. In the editor you see the traces brighter than the pour, but if you look at gerbers that is all solid copper.:
Of course, there are times when you want to restrict the gnd plane, like at a crystal, so define a rule area for “No copper zones”:
OK, thanks for your quick answer.
If you like (I like) you can change settings to have zones exactly the same color as tracks.
What is the reason to restrict gnd plane under crystal?
My question is in the kind: you learn all your life. I didn’t know such reason and never restricted gnd plane under crystals.
Crystal circuits are sensitive to capacitance in the pF region, so you need to account for stray capacitance or avoid it. Or use an active crystal in a can.
Ok found an application note that explains the effect:
I used to have a datasheet for an RTC chip that showed keepout areas under the crystal, but I can’t find it now. Now I’m sure I wasn’t imagining it.
OK. I understand.
My opinion.
It is practically only important for RTC with CL=6pF and IC designed to be used with crystal alone (without external capacitors). Thanks to 6pF you get lower supply current what is important for RTC, but you get higher sensitivity to stray capacitance.
If you use 12.5pF crystal the influence of stray capacitance is lower. I’m not sure but may be more lower than you can expect by comparing 12.5 to 6. I simply don’t remember details.
Long time ago we tried to precisely set our RTC. To get this I calibrated my frequency counter by measuring with it the perfect 1Hz (I was triggering the oscilloscope with 1Hz obtained from my RTC and observed at scope DCF carrier and regulated RTC (C trimmer) to make this carrier don’t move). I found my frequency counter had 4.2ppm error. Then we used this frequency counter to set RTCs at production.
If (for other crystal) I select to use C1 and C2 of 22pF or 27pF I ignore 0.2pF of stray capacitance and allow zone fill to go under crystal.
Well, stray capacitance is one aspect of a crystal layout, and would be more of an issue with an rtc oscillator, but I am just using 18-20pF parallel xtals of 8 to 25 MHz for a micro. I am not too concerned with absolute frequency accuracy, but more concerned with emi. I have done many layouts where I have not isolated the crystal area, and never had problems with operation and still pass fcc/ce radiation tests, so this is not mandatory. Isolating the top area keeps the crystal-freq/harmonic currents a bit more localized so the expectation is that may keep radiation and coupling to adjacent traces (antennas) down. I am unsure just how much it helps.
But best practices (many app notes) say to have a ground guard ring around the oscillator (not connected to top layer ground fill, which is why I have a rule area), keep the osc-in lead short, and just use a single via to tie the local oscillator ground ring and cap grounds to micro ground. I have a full solid ground layer just below on the inner layer 2. I have seen some folks recommend cutting this inner ground plane up at the crystal as well, but that seems worse to me from an emi standpoint. I have additional ground plane on inner layer 3 along with additional routing as needed, but I like layer 2 to be solid (well, split into digital and analog planes with a nettie, but solid with no signals cutting slots into it and affecting emi).
My crystal layout is likely not optimum, but works well for me.
I don’t remember reading any app note about crystal layout. My thought was that crystal (with those 2 capacitors) is a circuit of high goodness so needing only very small current pulses (coming from external) to keep it oscillating.
So if I lay out both capacitors just touching crystal and each of them connected with short tracks to crystal pads than all oscillating currents (there are rather no harmonic) are there. So if you have there more than one via you really can direct some of this current into gnd fill (never thought about it but for rectangle 4 pin crystal it was always easiest for me to place both capacitors with their gnd pins together and via there).
In wires connecting it with microcontroller I expect only small current pulses (these have harmonics) needed to sustain the oscillation. But it should be very, very small pulses as only energy lost during one cycle have to be delivered. So I assumed these has very little effect on EMC. Much higher pulses I expect for internal registers state switching) taken from blocking capacitors.
Writing the previous sentences, the following thought come to me. Crystals are designed to have the specified frequency when working with given CL. What if we don’t use capacitors. The frequency will shift. But will it be a big shift? I suppose not. For serial communication (RS232, RS485) to work correctly 0.5% clock discrepancy is acceptable. And (without capacitors) I would expect may be 100ppm deviation (it is 0.01% - 50 times less then accepted). If we don’t use capacitors the whole crystal oscillation current will be internal to it and we will have to take care only of small pulses in wires connecting crystal to IC.
May be it is the best EMC solution, or may be it whole is no problem compared with internal state switching currents.
I have used opening in top gnd fill (I was designing 2 layer boards) around switching L pad in DCDC converter. The 12.5x12.5 L has larger plates than the pads themselves and they are very close to PCB. So to limit the capacitance reloaded in each DCDC cycle I went out of this region with top gnd fill.
This topic was automatically closed 90 days after the last reply. New replies are no longer allowed.