I have several unconnected pins on my project. PCB Net inspector says they have very short tracks. Like this “/CM4_HighSpeed/CAM1_D0_P 1 0 0.0000 mm 0.0000 mm 0.0100 mm 0.0100 mm”
I can’t see any and the error does not go away with “clean up tracks and vias” tool.
Very short track segments should show up pretty much as circles.
Where did you get these numbers from:
If those (0, 0) are absolute coordinates, then you will find them in the upper left corner of your “paper”.
They are from “appearance monitor” /Nets, Show the net inspector. That was the only place I could get net lengths.
“If those (0, 0) are absolute coordinates, then you will find them in the upper left corner of your “paper”.”
No they are other part of track information. I hope this is clearer.
| Net Code | Net Name | Pad Count | Via Count | Via Length | Track Length | Die Length | Net Length |
|---|---|---|---|---|---|---|---|
| 26 | /CM4_HighSpeed/CAM1_D0_P | 1 | 0 | 0.0000 mm | 0.0000 mm | 0.0100 mm | 0.0100 mm |
| 27 | /CM4_HighSpeed/CAM1_D0_N | 1 | 0 | 0.0000 mm | 0.0000 mm | 0.0200 mm | 0.0200 mm |
If you click on any line in the net inspector, then the PCB edtor pans to that track segment and highlights it.
Or else, can you zip up and post a simplified section of your project with just a few footprints, as long as it shows these short sections it’s OK.
Edit: Oops, I missed that.
Good catch.
As you can see from your table, the lengths come from the “Die Length”, which is a property of footprint pads. It’s essentially the physical conductor length from the pad to the silicon chip itself (so the leg of the IC and the small gold wires inside the plastic housing and so on). If you don’t want that, change the properties of the footprint pads.
What has this to do with KiCad. Is KiCad really trying to use that small track for something. Simulation? Besides, it is a connector here, in this schema.
It is there. I can see it.
If you (Paul) still want to see simplified project, I can make one in the evening.
Die lengths seem to differ, one is 0.01mm and the second 0.02mm. I wonder.
I do not know how that 0.01mm has sneaked into your footprints, but such small distances do indeed not make much sense.
The pad to die is a valid extra length which can be significant enough for length matching. It should represent the total distance from the pad to the die itself. With for example old fashioned DIP40 the distance between the pad and the die of the chip can be over 20mm.
I see no additional benefit for that, Jonathan_Haas already found the root of your discrepancy.
I have no idea how that got into your connector footprint, but it’s for length matching. A chip can have two signals that are connected internally at different lengths. For example it might be possible that the internal connection of the CAM1_D0_N signal is longer than the CAM1_D0_P signal. Thus the length matching tools would include the “Die Length” in its calculations and compensate for that internal difference by making one external track slightly longer. Why this is on your connector and why the values are so small, no idea.
Maybe the Pi4 really has an internal signal length difference of 0.01mm between these signals. But probably that’s simply a mistake in your footprint.
I understand. My thanks to you both for solving this feature (not a bug, as Microsoft would say)
These kinds of details could come from Cern or something like that, but I would like to get a very well “polished” router. But that is an off topic here.
I think this is solved.
What has CERN got to do with that?
Isn’t Cern sponsoring KiCAD. They and other high speed designers could need exact timing. Allthough those devices I have seen have their deference plane there where the pins are soldered to the PCB.
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