Hi there,
atm i’m working on the KLC compliance of the 74xgxx lib.
And i want to violate the rules as less as possible.
But therefore, the symbols would change significantly.
Now i want you opinion if it looks usable or not.
Best regards,
Fabian
How could You touch my library! Just kidding… 
Well. The power pins ruins it all. Most of TTL era designers and Veribest guys expect PRE and CLR on the top/bottom. Now they meet VCC and GND in these places. Some unwritten standards should be preserved.
IMO it’s a bad idea putting asynchronous signals between synchronous, because this causes significant illegibility of this symbol.
Because there is a pressure to unhide power pins, the only best solution is to move them to the separate unit. This has some disadvantage - less significant in single gates, but until new schematic file format will be released, it can act as a acceptable workaround.
strong text`Thank you for your opinion!
the only best solution is to move them to the separate unit.
What do you mean with “seperate unit”?
I thought that there is only one unit..
Really, I have to ask why?
I would expect anyone working on libs to already know all about that…
I dislike inputs on the right side
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The KLC agrees with you! (as do I)
4.5.iii Input/Control/Logic pins should be placed on the left of the symbol,
4.5.iv Output/Controlled/Driver pins should be placed on the right of the symbol
I’ve been working on my symgen script, I am nearly in a position to automatically add a power unit to all 74xgxx symbols, needs a little fine tuning still.
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Given the recent move to IEC resistor symbols, displacing the more common IEEE (zigzag) resistor symbols, perhaps logic symbols should also be based on the IEC symbols. Datasheets often give the IEC symbol along with the more common non-standard symbol.
The IEEE logic symbols are also compatible with the IEC symbols.
According to these written standards pins such as PRE and CLR are on the left with the rest of the inputs.
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I’m gonna make myself hated again.
To be honest i can not read the current logic symbols. I learned to read logic symbols by programming in FUP (Siemens graphical programming language.) There the IEC style symbols are used. (Having a &, >=1, … marker in there makes it easier to read for me.)
For this reason my personal lib has the iec/ieee style symbols.
Heh, I was just wondering if anyone actually used IEC logic symbols.
As I mentioned before, my script could generate different symbols according to a template. Currently I have “traditional” symbols. It would be easy to generate an IEC library variant.
I also wondered about dropping the De Morgan equivalents, and making the “alternative” symbol the IEC version. Ideally, there would be an option in KiCad which allows the user to select a preferred “flavour”, and the symbols are selected accordingly.
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If one would like to use IEEE symbols falvour, there are ttl_ieee and cmos_ieee libraries…
I read the statement of bobc in another thread and therefore i will concentrate on new symbols.