In left schematic snippet, ERC complains that U303 pin5 input power pin is not drive by any output pin. (Note Pin 5 is actually pin 4, pin 5, pin 12 all defined as Power Input pins)
As this node is driven by a fuse, this seems fair enough as per my understanding of ERC. So add a PWR_FLAG seems reasonable enough. But ERC does NOT complain about U304 pin 5 even though its a separate node but identical layout and components and settings.
In right schematic snippet, if I add a POWER_FLAG to U303 pin 5 and a PWR_FLAG to U304 pin 5 (be consistent one would argue), then ERC complains that âPins of type power output and power output are connectedâ and also lists FLG#0301 and FLG#0302 as if it thinks both power flags are connected together?
Why inconsistent behaviour?
Why apparently link 2 flags together?
Something seems to connect both VCC pins and/or power flags together. Iâm not sure why this is the case, buit it looks dangerous. Are these symbols made by yourself? Make sure you have no invisible (stacked) âPower Inputâ pins on these symbols or other âweirdâ things.
Especially the following part about global labels:
Pins of electrical type [Output, Power Output, Power Input] are special cases.
Connecting Output or Power Output pins would result in an ERC error. Output pins that always need to be connected together must therefore be stacked. The invisible pins get the pin type passive in this case.
Invisible Power Input pins are global labels. This is to be avoided. For this reason the electrical type passive is to be used for the invisible pins in such stacks.
Firstly, thanks for responding - appreciate it.
Not my symbols - I just made slight mods to move pins around to make schematic more readable.
The 3 Power Input pins were stacked. Iâd made two of the pins invisible (just to make it easier to read). I see this is a âno-noâ according to the pin rules. I didnât pick that up or didnât get the significance of invisible meaning it became a global label. Because they were inputs I probably assumed it would be OK.
Making it so all three pins are visible produced consistent ERC error of no Power Output, and then adding the PWR_FLAG to both nets resolved that error as expected.
Yes, alternatively you could have made the invisible pins passive.
Invisible power pins unfortunately get some weird special meanings for historical reasons, I hope that gets changed in future versions, so global labels can be created more explicit.
In TTL times digital ICs symbols were not having power pins at schematic. They had hidden VCC and GND pins, and they were automagically connected without connecting them at schematic. I think in V5 some KiCad digital library still was made that way. I donât know how with V6 (I canât check it easily as I have only one Win10 PC and I have KiCad V6 installed with my libraries and not KiCads).
Thanks Piotr. Can see how this evolved âŚ
PS: You can always set up a virtual machine on your PC to test other software without touching your main machine. I use VirtualBox and its very helpful. Just delete it when you are finished, and build a new machine for the next test (or just set a snapshot and roll back!). Might be helpful for you.
I theoretically know that, but I have never tried.
With V5 I had:
one Win7 PC not connected to net (my working machine) and there KiCad with only my libraries,
second Win7 PC connected to net with default KiCad setup to help me check something people are writing about or to report a bug.
The first one I have changed to Win10 (KiCad V6 was the only reason), the second one I still have the old one. I donât need KiCad default installation on this isolated PC. I have Win10 laptop and I plan to have there KiCad default installation but (since 6 months) I canât find time to finish my Win10 setup.
The total time this laptop was âonâ since it was bought is less than 2h I think
