The four terminal resistor is used for current sensing, so you really need to be able to connect two nets to a single pad, without losing one of the names.
At the moment I have to overlap two pads and live with the DRC complaints
1 Like
Implement the pad similarly to how the pads of a net tie are made.
Or use the net tie itself.
This assumes your resistor is not already defined by the manufacturer in such a way that there is already a separate pad for the sense traces (a lot of shunt resistors really have a separate terminal for the sense connection)
A workaround at the PCB level is to add a trace on an unused layer[1]. So functionally, a part that is internally connected is equivalent to a footprint with traces on a “hidden” layer. Currently, DRC gets connectivity from actual copper layers. If the connectivity also got connection data for the “hidden” layer from the footprints, it can be added.
To add that information to the footprint, a group of pins could be selected and the property assigned:
- Not the same net (the current default if pin numbers are different)
- They are on the same net, but not connected internally (what happens if you give them the same pin number)
- They are on the same net, and connected internally.
- is the case that is new. That tells DRC only one of the pads needs to be connected to a net, the other pads in that group do not need to be. It also implies that if one pad in a group is connected to a net, all the other pads in the group are also connected.
I think this connection behaviour is not the same as pin or gate swapping, but I may be wrong.
[1] Obviously that only works for PTH, the principle is similar.
When I think of a 4W current sense resistor, I think first of those resistors you can buy with 4 actual terminals, such as http://www.vishay.com/docs/30189/wsk1216.pdf. I have also connected added sense traces to pads for 2W resistors, but I view that as something of a compromise.
Seems to me that for (mis)using regular 2 pin resistors as sense resistors, for how KiCad currently works one would want to use netties on the two sense lines. This would allow using a different netclass on the sense lines. (I doubt you really need current carrying (20mil? 30mil? more?) going to the pins of the sense chip…
I’m not saying that is ideal when using the “perfect” program, just thinking about what is available in the current toolset…
What do you think about my bug:
Ignore the touch key which was the reason I wrote it but later discussion went toward things like 4 pin switch. Using it for 0R bring to my mind now.
If footprint pads with the same number were considered connected then the 0R should have a special footprint with two pads just having the same number. Connecting such resistor to wire at schematic (one or two ends - not important) will allow to go that net through that resistor. You will not to have divide correctly the net at schematic into parts for both sides of 0R.
I think the problem with that is that the symbols (and footprints) should strictly follow datasheet numbering. You could of course not care about that, but I think the solution should make it possible while still allowing marking the connected pins.
First I will quibble with the idea of (mis)using a 2 terminal resistor. See this image from an IRC datasheet. This component in question is a low value 2 terminal current sense resistor. How are we going to deal with 6 physical pads making 4 nets? 
Beyond that…I will admit that I am not using net classes anyway. My attitude is that traces should be fat unless there is some reason to make them thin. My default resistor is an 0603 chip placed on 0805 pads, and I connect those pads with 0.040" = 1 mm wide traces where there is room to do so. Generally copper trace width is free in etched pcbs. In low voltage circuits, stray inductance and inductive coupling is the usual layout issue affecting performance, and wider traces are a little better in that way. There may be other exceptions where impedance control or capacitive coupling is of concern, but I do not run into those so often.
Hi, eelik
This observation may be out of date, but I recall years ago seeing contradictory pin numbers on SOT23 packages from different vendors. Caveat empty ( 
); a dose of caution is always wise with regards to pin numbers.
2 Likes
This is a part that I want to use. It only has two physical endcaps, but 4 nets are used, due to the sense traces. These part are used at around 1mOhm:
Yeah I know where you are coming from, I end up mostly ignoring the netlist trace width and just setting it manually a lot.
Hi, davidsrsb: That looks good. I am wondering whether that layout can work well with a pair of (are they net ties)??
A few years back I had essentially the same situation with a 2-terminal current sense resistor. I believe it was a 1206 package size. The mfgr footprint was similar to the illustration you showed, except it had only one pair of main terminals, with the sense connections off on one side. The intention was the same: the resistor end caps formed a bridge from the main circuit to the sense lines when the part was soldered into place. From the perspective of a KiCAD user the problem was the same: four distinct physical pads mapped to two electrical nets.
The details differ but we think alike. My employer’s default package size for passive components is either 0805 or 1206, and they sit on footprints with extended pads that are intended to make manual soldering easier. My default trace width is 15 or 20 mils (0.4 or 0.5 mm) with 15 mil spacing. Even though our board fabricator accepts 6 mil/6 mil as a “standard” job (and the surcharge for 4 mil/4 mil design rules isn’t huge). I have never had a situation where those smaller geometries were actually necessary, though I neck-down traces (8 or 10 mils (0.2 or 0.25 mm)) when connecting to pins on SOIC packages or passing a trace between pins.
Dale
Thanks, Dale
Yes with a 1206 (especially carrying high current) I think that trying to use 3 traces to each pad might be unwise. I am not sure of the benefits of 3 traces (as shown in my datasheet image) versus 2.
In addition to the lower DCR and slightly lower inductance (if I am using 1 mm traces both are probably of little or no consequence) there is the added consideration of mechanical robustness and withstanding a mishap which might break a thinner trace. I don’t remember a time when I ran a trace between pads, but I have designed a lot of boards with fine pitched LFCSP or 10 pin MSOP. Of course that geometry demands that traces at least neck down to 8 mils or so near the IC. My hands are not so steady and I hate soldering those but I can do it. BTW I am also in the habit of putting fatter pads (extended only outwards) at the 4 corners of the IC footprints.
@BobZ @dchisholm Do guys neck-down the traces manually or do you have a special method to do it? </off_topic>
Thanks
Well I suspect that men and women are likely to do it similarly.
When laying down a track, I right click and select (select track/via width) then (use custom values). I am doing it manually. I doubt that this is achievable in any automated way, but I am open to recommendations as to how that may be possible. Track width can also be changed later by double clicking on it.
That’s the component I created. Pay close attention how I split the pad.
zero_ohm_resistor.kicad_mod.zip (538 Bytes)
Hint: mod files are normal text files.
Cool indeed. The footprint editor doesn’t accept it, so it must just be made with a text editor. Furthermore, there’s no guarantee it will work in future versions. And it’s not explicit or self-evident, so not fit for public projects. But it wouldn’t be the first time someone uses “hidden” features of KiCad for their benefit. And maybe it can give an idea about how an explicit feature could be implemented.