Use a “Label” on a wire.
Then in Pcbnew, assign the node to a Netclass. It is quite easy.
If you have multiple wires that you wish to have the same netclass, use a easily identifiable names, like a prefix, that makes them easy to pick out of the list.
You may need to play with the popup for Netclass a bit. Use the right side node list.
I suspect V6 is about a year away now, we already had someone asking if there would be a V5.1.6, which there will be as there are non-critical bug fixes queued up
Why? Net classes are for physical design (trace width and space) while schematic is for logical design. It wouldn’t hurt have that data available in eeshcema, too, but I wouldn’t say it’s “right” to assign nets to classes in schematic side.
But it is the schematic where you see which wire is high current wire (to go to bigger width class) and which is high voltage wire (to go to bigger clearance class).
That’s true, and I agree the line between logical and physical isn’t necessarily clear-cut.
What I would like to see in eeschema is an ability to attach certain attributes to pins and/or components. For example, in the design phase when components are chosen, the current consumption is known. I would like to be able to tell that the output pin of the regulator must pass e.g. 500mA current and a receiving pin of another component take 100mA (implying that the track must be wider in the other end). Or a capacitor is a bypass for the MCU, implying it must be as close to it as possible. Then this information could be somehow used in pcbnew.
Adding data to components is already possible; how to use it in pcbnew is another thing.
But I don’t think this logical knowledge is 1:1 with the physical design.
Definitely agree! Of course, this implies that you have created net classes while still in the schematic (circuit design) stage of the project. To actually implement this feature, perhaps the “wires” in the schematic need to carry attributes defining minimum width and minimum clearance, and postpone the assignment to actual net classes until you start the physical board design in PCBNew.
And there is a prevailing problem that not ALL traces connected to a particular net need to have the same width. Consider a current-sensing resistor, for example. The traces carrying the rail current (several amperes) through the sense resistor MUST be wide. However, the traces carrying the sensed voltage to the sensing circuitry - the comparator, or in-amp which responds to the sensed voltage - carry a few microamperes or less. They do NOT need to be wide, even though they are in the same electrical net as the wide traces. (In ver 5.1.4, “net ties” provide a workable, though inelegant, solution to this problem.)
Back to the topic of specifying wire attributes at the schematic stage of design . . . . there’s a whole world of high-frequency and RF circuitry where wire attributes need to be specified at the schematic phase of the design. I don’t know if it is practical for KiCAD to address all of these requirements but there may come a day when a specialized version of KiCAD offers these capabilities.
Dale
Then there is the question of how to communicate the design requirements to the layout folk. Currently one can either put text notes in the schematic and/or have a separate document, or does one embed the information as object properties that requires digital access to the schematic? I’m not saying that I have the answer to this question…
Maybe I have luddite tendencies, but I like my dead tree carcass schematics…
Of course you are right.
But I didn’t insisted on implementing. I only protested against sentence that schematic is only logical design and has nothing to net classes 
This is opposite to my understanding of nets (wires that interconnect leads of different components or different leads of the same component). But I don’t know what SMD_Footprint means by net class, unless I missed seeing this term used elsewhere on this website. Perhaps this would be a good time to define this term, before continuing this discussion.
After reading the post at How to set trace width, clearance I gather that a net class is a physical implementation of a net, that is a trace of copper with a specific width and a specific set of (x,y) coordinates starting at one end and proceeding along the trace to its other end. Or is a net class rather that set of trace widths already entered into kicad which appear when you click the “Board Setup” icon in pcbnew and go to “Net classes” under Design Rules ? I am still not clear.
Net class is a way to set physical properties of tracks and vias which belong to chosen net or nets. In the Board Setup/Net Classes you define a net class and add one or more nets to it. The tracks and vias which belong to those nets which belong to that class have those physical properties as defaults. The nets which belong to the same net class don’t necessarily have any logical connection, only the physical properties. A class can be “Power” or “Signal”, but it could be “Wide” or “Narrow” as well.
Basically it’s just a way to bunch several nets together for the purpose of setting their default physical properties. Without net classes you would have to define the values for each net separately.
Oh, so net class means that set of attributes that describe one particular trace on one particular board connecting one particular net, but could be replicated for other nets. (For example, a power & ground net class, a high-amperage DC motor net class, and a control signal net class.) I guess that set of attributes would include layer and width but not (x,y) coordinates of points on the net nor board layer. The net class attributes would be those attributes shown in pcbnew under Board Setup…Design Rules…Net Classes, namely Name, Clearance, Track Width, Via Size, Via Drill diameter, Microvia Size, Microvia Drill diameter, dPair Width, and dPair Gap. Presumably each of these attributes would be identical everywhere on one particular net instantiating those net class attributes. Thank you, eelik, for clarifying the term “net class”
Is there a limit to the number of net classes in one particular project ? If yes, is that limit the number of nets in the schematic? Or does the kicad PCB designer have the ability to predefine as many net classes as he feels could possibly be needed by his project ?
You’re overthinking this. Net class is simply a set/group of nets that you want to identify with one name, then you can assign attributes to the set/group in one go. So the max number of net classes is the number of nets, where each net is in its own class. Forget about class in the OO sense, think set or group.
I understand it completely different. Net class is the simplified way to specify some parameters to many nets instead of specifying them to each net separately. So it is only the way to save your work.
Not in KiCad I used to specify 3 classes of elements: Small, Medium, Big. Then I inserted electrolytes, SMBs (by their references like: C3, C7, D8, D11) to Big class, SMA, 1210, 4,5mm inductors to Medium and rest (mainly 0603 and 0402) to Small. And then I specify thermal connections for BIG to be 30 mils wide, for Medium to be 20mils wide, and for Small 10mils.
You can specify thermal connection width for each element, or each pad, (you can have a hundreds of them) but simpler is just to specify it once for classes (I have only 3) and then assign the element to right class.
About net classes may be in future you will be able to specify for example a class Isolated, and then put there all nets of isolated part of your schematic (I think of isolated RS485 for example). Then you will be able to specify the clearance not for nets in that class but to specify clearance between any net in class Isolated and any net not in that class.
In my opinion assigning clearance to net (net class) is a wrong assumption made probably when KiCad was born. Clearance should be specified with From … - To … .
There has been talk about having an advanced configuration, it would have a matrix of values.
There is also talk of creating a physical design language to manage all of the details that usually wind up in engineering notes. Rather than a note that says to match lengths for two lines you add that as an attribute and a DRC will fail if they do not match.
Just yesterday I was kludging a circuit segment onto a solderless breadboard. The most challenging part of the task was getting a paper printout of the schematic. (My employer recently revised the network, replaced old printers, changed “security”, etc. I had to mess with permissions, user profiles, default configurations, et al, just to print an American B-size sheet (11x17; “Ledger”).) At one point the IT guy asked why I even needed the printout, since I’m doing boards and schematics with computer programs. Well, as I built up the circuit I marked the components and connections with a highlight marker. I don’t think he would have appreciated my using the highlighter on the computer display screen!
Dale
This will be possible with the implementation of net ties as first class tools (At least if i remember the discussion correctly)
Hasn’t anyone here used Altium before?? Not that im saying altium is the be-all-end-all standard but it does (and other packages too) do a lot of things rights. One of which being net classes…
Defining them in the schematic is just good practice, simply put. To me schematics are like code, it should be well documented no matter who is looking at it. These net classes should be transferable to/from the pcb design. The net classes should be able to define a myriad of things/rules for the DRC/Fills/etc. as guides to follow.
I personally use net classes and rules everywhere i can. I primarily use them for length matching, differential pairs, clearance, widths, layers, and even vias.
Altium for sure is a good inspiration source but i would not copy it fully. After all kicad can at best be as good as a software it copies.
I am not so sure i would define manufacturing specific things inside the schematic (absolute minimums of width, clearance, …).
However, a way to define the requirements for potential classes (increased clearances) would definitely fall in the responsibility of the schematic designer.
But even here i would not really burden the schematic designer with directly setting the clearance in “mm”. It does not only depend on the voltage but also the materials used in pcb manufacturing (and the layer the trace ends up in). All the layout side really needs to know is what the voltage is of a specific net and then the manufacturing parameters are used to derive what clearance is required.
Similarly, for width and via size as these can be derived from the current, maximum voltage drop and temperature rise. Here again the manufacturing parameter “layer thickness” comes into play as well as trace length and of course the layer. (All these things are not known to the schematic designer.)
Agreed, and I wouldn’t want it any other way. That’s also not what I was after with my comment. Just merely pointing out that other tools offered some facility to transfer information from schematic to the pcb layout.
Also agreed. However I still think some minimal information still needs to be transferable to the PCB designer. Things like differential pairs and impedance controlled signals just to label a few. This information could at the very least be carried by net classes which pre-groups them. Which in Kicad’s current state (as far as I can tell) can not create net classes in the schematic for transfer. It currently seems to be a manual step for the PCB designer to find and select the correct nets (if they were even labeled correctly) to be classed. Which IMO, could/should fall under the practice of an schematic designer.