I’m extremely new to KiCad (and PCBs in general), but I’ve handled things well enough. However, I’ve been copying and pasting track segments on top of each other to speed up repetitive placement. All the tracks are the same type, so I don’t worry about real-world issues, but is the length calculation going to be messed up by this? I’ve included an image to help explain what I mean.
It’s two segments of wire that have a huge amount of overlap. Both have the same length, so will the length calculation take both into account? If so, how can I erase the overlaps without breaking the loop?
Trying it out would have been less work then typing your post.
In KiCad, the goal is to calculate the real copper length, but actual behavior depends a bit on the KiCad version you use. KiCad also has: PCB Editor / Tools / Cleanup Tracks & Vias / Merge co-linear tracks In a future KiCad version, the goal is to predict actual propagation delays, which also depend on how the PCB is build up.
Overlapping segments will cause an incorrect determination of track lengths; the tool that @paulvdh has highlighted will fix up your layout.
Also of note, the nightlies (which will become v10) can now calculate / tune time-domain propagation delays.
