Will Kicad support for Micro via routing for WLCSP package .4mmpitch and 0.265mm pad dia
The dev team has far fetching plans for router development, including improvement in stackups and via management. I am not sure about exact dates and features, you can check developers mailing lists for more info.
for example this thread https://lists.launchpad.net/kicad-developers/msg14762.html or this one https://lists.launchpad.net/kicad-developers/msg14783.html
I am using 81 pin 9x9 WLCSP package. The pitch is 0.4mm,and pad dia is 2.65mm.I have to fan out all the pins in 3.5mills spacing/trace width, but i couldn’t, even grids were in metric units.
Following are the ways i tried:
I am unable to put stacked micro via,since kicad doesn’t supports micro via in the inner layers. So, i tried of using buried via. since the pitch is 0.4mm i can’t fan out some 15 pins in center. So i used VIP technology(via in pad). micro via(1-2 layer) on land and i tried of putting buried via on same place(2-3), kicad is not allowing me to put buried via on the same place(beneath micro via),means stacked via.
So please suggest some solution to fan out all the 81 pins in 3.5mills spacing/trace width. Or else please send me some sample Gerber which will help me a lot.
I am pretty sure Kicad cannot do this yet, I don’t know when (if anytime) these features will be available in future builds… I suggest to ask this question in the kicad-dev list?
There are quite a lot of examples of fine-pitched BGA packages breakouts on the net, like this one http://www.latticesemi.com/~/media/Documents/ApplicationNotes/PT/PCBLayoutRecommendationsforBGAPackages.pdf?document_id=671
They have your 81-pin package breakouts described in this document too.
I am also using 81 pin 9x9 WLCSP package. Are you successfully routed all the pins…? And please let me know how to fan out all the pins in KiCad.