maybe I used the wrong search terms, but a brief search through issues and forum threads didn’t reveal much details about the planned padstack feature.
I would like to know whether a pad stack for a via will allow also to set the solder mask for the via.
Reason: The “tenting” settings of KiCad don’t allow to keep only the hole free from solder resist.
Covering plated holes with solder resist is generally a bad idea, since the PCB finish (HAL, ENIG etc.) doesn’t reach the inner side of the hole, and residues from process steps are not cleaned properly (trapped in the hole by solder resist). I have seen long-term failures in the field caused by this issue. Surprisingly, this topic is often ignored.
“Do not tent vias” uncovers the whole ring, which is bad if vias are close to pads or other vias.
The best solution is to uncover just the hole, so the ring edge is still covered, but the hole is open to be cleaned and reached by the surface finish process.
No, this is not possible in KiCad today (or in the upcoming V9). You could create a feature request for it, though. I haven’t seen one before.
Right now, vias in KiCad (unlike pads) cannot have a specific solder mask override diameter set. So it is not possible to set the solder mask aperture to something other than the diameter of the via pad. In V9 you can control the solder mask per-layer (for example, tent the top but not the bottom layer) but you cannot (for example) set the via as untented but with a negative solder mask expansion override (to make the solder mask aperture smaller than the via diameter) which sounds like what you want.
that’s not exactly what I want, but close. The solder mask shall just spare the hole, so the hole diameter is the relevant parameter, not the via diameter.
An example: A hypothetical via with 2mm diameter and 0.2mm final hole diameter should get a solder mask diameter of (0.2mm + manufacturer_defined_value), not (2mm + negative expansion).
You can use it to implement what you want. In KiCad, solder mask is always defined relative to the pad copper size (not the hole size). So in order to get solder mask that is slightly larger than the hole, you need to start from the finished pad size (not the finished hole size) and subtract something.
Do I understand correctly that KiCad 9 will have a setting to get solder mask expansion override only for vias?
This would be great starting point since it would allow a setting “cover just the borders of a annular ring with solder resist”.
However, the underlying manufacturing requirement is “do not contaminate the hole with solder resist”. IOW it’s related to the hole diameter instead of the copper diameter. In my opinion, that’s more straightforward.
Let’s have (exaggerated example) vias “0.3mm hole 0.6mm diameter” and “0.3mm hole 1mm diameter”.
No. Like I said, KiCad 9 allows you to control the tenting on the top and bottom on a per-via basis, but it is all or nothing. There is no expansion override for vias.
Maybe with this point of view, yes, but this is not a popular feature request (yet) and it’s not the way it works today. I suggest opening a feature request for control of the mask size for vias.
I know, it’s a pity. This important requirement is ignored by most developers. The communication back from the PCB manufacturer specialists to the developers is “complicated”:
Most developers never come into contact with PCB manufacturers. Purchasing and sales departments isolate them.
The PCB manufacturer doesn’t want to criticise the customer.
The manufacturing experts shall not waste time to discuss with customers.
I have personally never experienced this issue. Any PCB I’ve made that has to deal with high humidity conditions gets conformal coating, which I guess makes the solder mask question kind of irrelevant?
I wouldn’t dare to try. Besides: There are usually no drawbacks to open the hole and let the PCB finish enter the vias to cover the copper (unless you use a vacuum test adapter).
"…hole of the Via is to be covered with SM. This is ONLY possible in conjunction with Via Filling
[…]
Also, there will be SM ink inside the via barrel and residue may remain after exposure and curing of the SM. This can lead to numerous issue such as bad SM adhesion around the holes or if this residue becomes lose it can cause a bad final finish plating of the component pads due to chemical fluid entrapment etc.
To avoid to these potential issues, we always open all holes (NPTH, PTH and Via Holes) to be free of SM."
I think this is a request you should forward to your manufacturer. Since they know the actual drill size, plating thickness and tolerances of their processes. Otherwise you will end up with a partly covered hole or sauce in the hole anyways. The manufacturers I’m using mostly (Eurcircuits, Würth) do this automatically by the way and don’t print over vias.
