Hi,
How should I handle trace widths/connections to pads when the widths are larger than can be connected to the pad?
For example, this transistor is rated to 4A continuously in a SOT23 package. The PCB calculator tells me to use a trace width of ~2mm,but that can’t be routed to the pins due to space constraints.
How do you handle this?
It is rare to actually run a device at the ratings limit, usually on the small package parts thermal considerations come into play.
Plus these days, it is common to find the ‘price minimum’ is rated well above what you actually need.
That said, if you do need to push highest current into small packages, that is usually done using filled copper pour areas. That also helps with cooling, as you want the highest copper plane cooling all the device leads.
To create a fill area, you tag the pin net name, onto the fill polygon. The fill area outline edges can be rough, as the fill clearances will pull those back automatically from other traces.
Check the device data to see if any pin has priority - ie if the die is mounted onto the collector leadframe, and wire-bonds to the other pins, the pin you want to cool the most is the collector.
I guess the answer you are looking for is neckdown…
search this forum for neckdowns related threads…
i guess even @PCB_Wiz has posted regarding neckdowns somewhere 
I do mostly audio designs where this comes up a lot. I normally run a wide track up near the pad and then do a manual neck-down by drawing a zone between the end of the track and the pad.
In this example (using a Lovoltech JFET in a TO-251) the power tracks are entirely zones, but you get the idea:
Thanks for the input!
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