Why kicad 6.0.5 copper clearance is between via's hole and copper?

The via is set ‘‘start end and connected layer’’.
In 6.0.2, the copper clearance is between via’s diameter and copper.
In 6.0.5, the copper clearance is between via’s hole and copper.

What OS etc
I am using the most recent “Testing” on Windows, which is only a little ahead of 6.0.5 and zone clearance is to the via copper as you would expect

There where some changes/bugfixes regarding zone-calculation involving vias on >=4layer-boards between v6.0.2. → 6.05.

To decide which of both pictures is the “correct” calculation is not easy with your pictures - please attach the archived project showing the detail of your via.
(As a new user you probably need to first read some posts to get an upgraded user-thrust-level before you can attach something)

left pictures(6.0.2) is the “correct”.

left pictures(6.0.2) is the “correct”.

Yes - for you (as you expect this result from the old v6.0.2-behaviour).
But it’s impossible to judge from the pictures were to look for the calculation difference.

You have gained the basic-user trust level during the last hours, so you might be able to attach the zipped project-archive (project-manager–>file->Archive).

For me right picture looks more “correct”.
The ‘black’ ring around via is probably clearance used for zones. And it is the same at both pictures so you accept it as being correct.
The zone in question exactly touches that ‘black’ ring at right picture so looks for me correct.

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Why do you think so?
Why would the clearance form a via have bigger gap then from the rest of the zone boundary?

Looks like a bug in calculating via clearance was fixed in KiCad V6.0.5.

viatest.zip (107.9 KB)

I think,the via is set ‘‘start end and connected layer’’,the copper clearance is between via’s diameter and copper,not between via’s hole and copper.
picture1 is in1 layer gerber

picture2 is in1 layer

The ‘black’ ring around via 12mils(between via’s hole and copper)

Clearance must be effective from the via’s copper to the other net’s copper. When “Start, end and connected” is selected this means that in non-connected layers the clearance is from the hole edge, not from the via’s nominal copper diameter, because the via copper exists only in the edge of the hole and there’s no annular ring. This is logical and commonsensical. Otherwise having the “only connected” option wouldn’t make sense at all, we could as well have the annular ring on all layers.

I took your viatest.zip and looked inside. Seems ok for me:

  • clearance-distance between zone and via-copper is always 0.25mm
  • for via with copper on all layers (no-net-via on top of board)
  • for the other 4x vias (with annular rings on top, bottom, inside: only connected layers) the distance is between copper-zone and via-hole and seems also ~0.25mm

Looked again, there could be an error at marked place (see picture).
@xuqm : do you mean that point?
@ others: I think there is too few clearance, but I’m not sure.

There is definitely still something wrong with vias and setting “start, end , connected layers”.
I have changed the “problematic” via to 0.4mm/0.9mm (hole/diameter) and this clearly shows to few clearance. Added an “standard”-via as comparison.

Looking again at gitlab (I knew there was something regarding via/zone …) revealed issue nr. 11299: PCBNEW: Pours don't obey clearance if unused via pads are toggled off (#11299) · Issues · KiCad / KiCad Source Code / kicad · GitLab
Currently still not solved, and looks like it will take some additional time.

The problem is exactly what you said

The problem is exactly what @ mf_ibfeew said.In 6.0.5 ,the clearance are not from the via’s copper to the other net’s copper,when “Start, end and connected”.But in 6.0.2 clearance are from the via’s copper to the other net’s copper(i think correct)

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