Why does DRC flag pad near pad for non-copper layers?

After running a DRC check in PCBnew on my board layout, I get a host of ErrType(19) Pad near pad errors for non-copper layers. I understand the pad near pad error, but why would I care about non-copper layers?

maybe they’re for solder masks or paste masks where you have minimum distances to obey?

1 Like


Probably your silk print is on the pad. No good for production, some fabs will ignore, some not. As a rule, there should be no silk print on pad. Hard to solder, etc.


Thanks Tom. Makes sense. However, these are footprints from the Kicad library. Are these footprints reliable or does one have to review each one?

Does DRC moan about pads of different parts or of pads within a part?
Do you have an identification of the part in question?

Oh, sorry for not being clearer. Yes, DRC reports pad near pad for pads within the same part.
ErrType(19): Pad near pad
@ (81.314 mm,53.523 mm): Pad 6 on F.Cu, Non-copper of Q1
@ (81.965 mm,53.523 mm): Pad 5 on F.Cu, Non-copper of Q1

Attached one of the footprints with the pad near pad on non copper layer error.

sot323-6.kicad_mod (2.0 KB)

Oh of course the libs are great, in general.
I always check them, because there are many use cases. Hand solder, reflow etc…
Special footprint arrangements for thermal issues…

Most of what I have been doing is surface mount and small pitch… reflow solder. Where can I find guidelines mask spacing for various solder methods i.e. hand, reflow, wave etc.? Thanks!

I think that squawk is telling you there is a clearance problem between Pad 5 and Pad 6, and that those two pads are defined in some non-copper layers as well as the top trace layer ( " . . . Pad 6 on F.Cu, . . . ")

There’s only about 5.5 mils (0.14 mm) clearance between the pads in that footprint. What are your design rule values for clearance of the nets associated with Pad 5 and Pad 6?


Pad “Local Clearance and Settings” for all 6 pads of Q1 are set to 0 ( parent or Global values) and Copper Zones pad Connection is set to From Parent Footprint. Net design rules for Pad 5 and Pad 6 are Default and are as show

That seems to be the explanation for the error message: DRC wants to see at least 0.2 mm between copper features in those nets, but the footprint provides only 0.14 mm. There are several possible approaches to the situation, including:

  • Specify a narrower width for the footprint pads. (You do the arithmetic to decide how much narrower.) Be sure to leave enough pad to get a good solder joint on the specific component you are using, especially if it will be hand-soldered. You may want to consider various manufacturers’ suggestions for a suitable footprint - most of them recommend a narrower pad than what is used in your footprint.

  • Change the DRC constraints, at least for the nets connected to that footprint. I see that your “uHDMI” net already tolerates closer spacing. Of course, your board fabricator may refuse the job, or charge a premium price to guarantee success with the closer spacing. Even after the board is fabricated, the assembly process (whether manual or automated) is more susceptible to solder bridges when copper features are spaced more closely.

  • Do nothing - i.e., ignore the DRC squawk. It may be the result of a faulty layout program, raising false alarms on your board. Or perhaps you have lived a righteous and upright life, exhibiting integrity and generosity in all your affairs, so the Almighty will grant special favor to this endeavor of yours. On the other hand you may have even sold your soul to the Devil, and in exchange he will use supernatural abilities to ensure your successful outcome.