When Spice model netlist export will be released?

Hi all,

As from the title I would like to know when and in which release will be released the feature to export a schematic netlist as a spice model (subctk).

I saw that in the main branch on gitlab there is the class to allow this feature.

Schematic to spice netlist is already an existing feature in 6.0?

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Yes I know,
I’m speaking about a spice subctk model. Basically it’s a syntax allowing you to add a model that later can be used in other spice spice programs as a component.

Here a small reference

So this feature will allow kicad to be used to model subcircuits that later can be used in more complex schematics for simulation.

You may create subcircuits from Eeschema drawings right now.

Draw a circuit (to becomer a subcircuit). Export it as a ngspice netlist (see post by marekr).

Then add two lines: a .subckt line on top and a .ends line at the end.

The .subcircuit line starts with .subckt, and then the name of the subcircuit, e.g.

.subckt vdivide

What now is missing is the nodes for interfacing the subcircuit. They have to follow the subcircuit name and have to be equal to nodes of your netlist (typically the inputs and outputs of your circuit).

.subckt vdivide node1 node2 ... nodenn.

If your circuit is a voltage divider

*voltage divider
r1 1 2 10K
r2 2 3 5K

and you want to access all of its nodes (named 1, 2, 3 here), the subcircuit line now is
.subckt vdivide 1 2 3
and the complete subcircuit may look like

*voltage divider
.subckt vdivide 1 2 3
r1 1 2 10K
r2 2 3 5K

and you may call it from another spice netlist as your model of a voltage divider by
Xvdiv in out gnd vdivide
or by putting it into a file voltage-divider.lib and attach it to your (tentative) voltage divider symbol.
Even if Eeschema would finally have the button ‘create subcircuit’, one would have to tell it what name the subcircuit should have and what nodes are to be interfaced.

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Thanks for your advice,

I am currently doing it like that, but it’s tedious because it’s an action that could be easily automated.

I was creating my self a program to generate a sub circuit using some regex to find out the input and output nodes (given by labels), I was trying to make it work taking as input the XML intermediate file generated by kicad and creating a custom generator…

Unfortunately in the XML file there is not the information about the text label in the schematic and that was blocking me because without them it’s practically impossible to generate some circuits (e.g. a transformer).

Looking the source code to add this information I discovered that someone already added the feature to the main and that’s why I thought to ask when the next release is planned, to understand if it is worth to work on that my self or if I should just wait for the maintainers to deliver this feature themself.

Next year, hopefully January, no guarantees.

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Thank you, I’ll create a stupid script in the meantime and I’ll wait for it to be release


Like the OP and particularly IC designers (like me), I too wanted hierarchical symbols within Kicad that would be able to create a simulatable hierarchical spice netlist using a methodology similar to mainstream IC design EDA tools. As this capability does not exist natively in (the otherwise quite excellent) Kicad I set about creating it myself.

This turned out to be quite an undertaking and this is the 1st time I am sharing this. I am still testing and debugging but this flow is fairly solid now. I follow an approach that allows user defined hierarchical symbols in schematics. Each hierarchical symbol can point to an underlying schematic or a spice netlist. Parameter passing from symbol to schematic is allowed. It works very much like a Cadence or Mentor IC design flow.

To enable this, I wrote my own spice hierarchical spice netlister that starts at the top Kicad simulation schematic and then searches through all underlying symbols/schematics to determine the full design hierarchy. It then converts this to a hierarchical spice netlist with correct pin interfaces. Making this fast proved to be quite challenging (at least for me).

The overall design process, netlisting, simulation, etc is controlled by a framework called ConfirmaXL. Confirma is similar in operation to Cadence ADE. Confirma now includes an ability to navigate the Kicad schematic hierarchy (you can select and open a lower level schematic after completing the hierarchical search of Kicad top level schematic).

Confirma also allows various spice simulation plugins such as ngsppice, topspice, smartspice etc. The spice netlist is passed to the chosen simulator when the simulator button is pressed.

So far, I have constructed some fairly large subsystems in this flow. These include behavioral and transistor level plls and RF transceivers. A fractional synthesizer composed of 18 pages of hierarchical schematics was designed and simulated in topspice and then again in Sandia Labs xyce. The plot button can be set to the chosen plot tool. I am using topview.

Previously, the Confirma flow utilized a Mentor DX design schematic front end. That changed when Mentor dropped the ascii format for the schematic files. It is the text format (and relative simplicity) of Kicad schematic and symbol files that has made this effort possible.

I am hoping the schematic/symbol files in version 7 doesn’t change too significantly as that would be a major setback to my efforts.

I am adding a representative picture of what the kicad/confirma/spice flow looks like.

You can see the resulting hierarchical spice netlist of the design as presented in one of the confirma tabs. Pressing the “netlist” button starts the netlisting process with the refreshed netlist presented here. The spice simulation control statements are also set within Confirma.

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