What isolation/clearance settings are people using for ground pours?


Hi All

So this board…

Works fine on breadboard. It’s an ATMega328p with an ESP12.

The goal is to use the ATMega to write sensor data (temp, humidity etc) to the EEPROM on the RTC module and then go to sleep every minute (or 5 mins or…).

Every 10 mins (or 20 mins etc) I want the ESP12 to wake up, become the I2C bus master (yes funky I know but I’ve found ways to do it here https://www.hackster.io/chipmc/arduino-i2c-multi-master-approach-why-and-how-93f638), read the data in the EEPROM and dump it via MQTT.

The reason for doing all of this is battery consumption. I want to use uA when sleeping and low mA when reading sensors. I want to be able to control how/when the esp12 wakes up.

As noted above, this all works fine on breadboard. When transferred to a PCB, it’s all goes pear shaped…really odd behavior, atmega crashing, I think I’ve blown the atmega in the latest build and it looks like i’ve shorted gnd and vcc and yet it’s not a soldering problem i can see (i’ve been doing SMD for a while and it’s normally fine).

There’s no voltage regs, but powering from a LiFePO4 battery or a bench top PSU yields similar results.

I’m thinking my ground pours might be to blame, not enough isolation perhaps ? I’m using PCBWAY as the manufacturer, but following OSHParks settings. Everything passes DRC and ERC in Kicad.

I’m stumped, any comments or critiques welcome…


You need a much more clear explanation for help.

If in fact, your vcc was shorted to gnd, and you used a good, fully charged, battery, then any short would be evident by smoke signals.

You also state that you used a bench top PSU with “similar” results? A battery does not current limit, while a good lab grade power supply will have selective current limit.

First, I would double check everything under magnification.

Then, I suggest you use your PSU and report back here what your voltage and current is while the board is powered on.

With good technique on your part, I can help you troubleshoot the problem.


Carefully inspect your board under magnification. If the raw board is cleanly etched around the ground pour - including ALL of the pads and traces within the pour zone - and if there are truly no solder bridges, then the isolation is adequate. My eyeball estimate is that your ground pour clearance is set to 10 mils. This is more than enough for modern automated reflow soldering, although for manually soldered boards I try to work with 20 mil spacing between any copper features, and 20 mil trace widths.

What does your ohmmeter tell you about the assembled board, with no power source connected? Is there a short between GND and a power rail? Is it there with either polarity of the ohmmeter leads? If so, go back under the magnifier and look again before using your time to consider other possible faults.

If there are no assembly errors, and no fabrication errors, you are left facing a design error. There are a few checks you can make quickly.

  • Generate a new netlist. Import it into PCBNew. Re-run the DRC. It should be clean.

  • Use the “Highlight Net” tool (in PCBNew) to highlight the GND net, then each of the power nets. Look carefully at the display to see if any highlighted pads or traces should belong to a different net. If so, there is probably a schematic drafting error.

Schematic drafting errors are sometimes difficult to find when I look at a *.pdf plot of the schematic. It may be helpful to post the actual KiCAD schematic file.



I won’t ask how you learned this . . . . :wink:



Are you sure the ESP8266 IC can’t be programmed to do this on it’s own?


Running an AVR to run the ESP8266 for power saving purposes is an ugly hack… and then an EEPROM to transfer the data… in Germany they call that: “Mit der Kirche ums Dorf”.


Any long term electronics person can read ancient Indian smoke signals.

What is really fun is when your newbie tech assigned to your work cell has a short on the 5V line of a board with 20+ chips on it; and you bring them the 30V/30A power supply to show them how to find the problem…

Oh yea, we’re gonna do this! :smiling_imp:


Next question, what footprint for the ESP-12 module did you use there?
Why the PTHs for the horizontal pads?

Then your GND ‘plane’… it’s completely shredded.
You have no consistent approach to make sure it resembles a plane at all.
There are large swatches that are connected to GND via thin dams to other GND areas only… it’s a nightmare - EMI wise.

Then the antenna area… I would get rid of the RESET stuff in the top right there and retract the GND planes all behind a vertical line that you keep in the area of the ESP-12 module itself.

Also, why so large clearances for the GND plane to it’s own pads?
Do you hand solder or reflow?
For reflow you don’t need thermal relief, definitely not so large ones.

In future…
Personally I would use 0.25mm tracks for everything as minimum, not what you got there (I usually go 0.3mm).
Then make yourself use the back or the front as GND plane and only lay tracks on it if you have NO OTHER CHOICE.
And even then, try to keep those tracks short, to not to disrupt the plane and cause large swatches that need stichting with planes on the other side to get the plane ‘monolithic’ again.
Use VIAs.
Keep tracks away from the antenna area of the WiFi module at ANY cost.
Stich top and bottom GND plane on that vertical line there together.
Get rid of the 45 deg rotation of the AVR - you got lot’s of space on that board and don’t need to use such measures yet - it disrupts your layout and you’re not experienced enough to make proper use of it.

My filled-zone(s) settings for those GND planes you see there:


OK, so I haven’t actually seen a short, what I did observe was 500ohms resistance between GND and VCC (but open circuit the other way),

On my reddit thread here

Folks have suggested that is probably current flowing back through a transistor.

Before I connected any battery, I did test extensively with my bench PSU, and current never got above 10’s of mA, so the battery should be fine (and no smoke has escaped thus far :slight_smile: )

I’ve had plenty of feedback that my power distribution needs to be thicker/shorter and probably more via stitching the two ground planes.

What I was after from this forum is what sort of isolation/clearance settings for ground pours do people generally use ?

Secondly the Kicad track width calc for 300mA (absolute peak current by my calcs) for 50mm for a 20deg temp rise indicates a 0.046mm (lets say 0.05mm width), does that sound about right ?

Edit: Scratch the questions, Joan_Sparky has answered them !


Yes ! This is what I was after thank you !
I’m totally self taught (well non practicing EE) in this area so there’s a heap I don’t know ! As my designs progress from simple to more complicated stuff like this starts to bite me.
I’ll take your advice and have another go at the board.
Yes I thought the ESP footprint was odd, but didn’t really question it, as it fits (can’t remember where i found it)
I hand solder but I’ll get a toaster built one of these days and get into reflow.

Thanks again.


So that example has a 10 minute resolution, I’d like to be able to have a 1 min resolution and only upload every 10 or 20 or 30 mins…I realise it’s ugly, this is a learning exercise for me on a number of fronts (and your other comments below are a great help). An ESP32 would do all of this without blinking but AFAIK there is no sensible way to wake an ESP8266 and not have it consumes 30-40mA (let alone when transmitting). Do that every minute and a battery is shot.
Yes there are other non WiFi options but they need gateways etc.


Check out low power ESP8266 designs, I’m sure the radio (which is the power hog here) can be controlled via programming and siwtched off if not used.
Ditch the AVR stuff and make your design simpler… just the RTC, the BME280 and the WiFi module.
Less points of failure and once you got the hang of the ESP8266/etc. thingy you will know what I mean.
There is a dedicated community for that… http://www.esp8266.com/
I’m sure they will be able to get you sorted out on that front.

As for your layout…

Try to group devices together after importing them into PCBnew via netlist loading.
Move them around and build small groups of stuff that belongs together.
Wiring between them inclusive.
Get them aligned a bit (side by side), so that when you solder you have them all easily accessible with your iron from two sides only and don’t need to care in the other directions.
Placing them all over the board under weird angles makes your job needlessly harder.

Place the buffer capacitors as close to the VCC pins of the respective ICs/modules as possible. Have them connect to the GND with a VIA.
If you distribute the power, don’t be afraid to use 0.8 or 1mm track widths, you’re not pushing limits here. The copper is on the board anyway, make use of it and don’t stick to the minimums. The bigger everything gets, the easier it is for the cheap fab to make it work for you.
For all other tracks use 0.3 mm so the cheaper fabs can screw up without your board not working (and yeah, i’ve seen half a track missing @ 0.3 mm :wink: ).
Use 0.4 mm vias… 0.7/.8 mm annular ring diameter as minimum.
Again, if they screw up, you won’t notice.

If you hand solder keep the thermal relief for the filled zone settings. If you do reflow you can omit them. This get’s more important for really large designs, as they’re there to make it easier for hand soldering, to not wick the heat away…

Learn how to make footprints yourself. It’s pretty easy and the more you make the better and faster you get.


On the ESP8266 front you cannot go into deep sleep and wakeup without doing a complete reset of the board losing any state you may want to have/keep.
Even with WiFi turned off, it’s still consuming 40mA
And it takes a long time (hundreds of ms) to even get to a state where it can turn the WiFi off and read a sensor from the reset. I’ve spent a long time on esp8266.com :slight_smile:
Thanks for all the other tips tho…this is what i need


Cool, thanks for that feedback. I’ve not used them much - had some samples, but never got past initial tests.

Next cool kid in town seems to be LoRaWAN (low power - battery, long range), which catched on with a couple of people in my field, so I’ll probably do something there in due course.
Already searched around for a 32bit based module with radio+mcu, where the access to the mcu is available and can be used for custom programming (as I was used to from the Meshnetics ZigBee modules).
Already found an STM32 based platform and a thing called radino32 SX1272 which must have been derived from that - so all open tools and the potential to have more people use it as well, which makes stuff easier.


Hi, so I’ve tried to follow your guidance…power traces are now 0.6mm, signal traces are 0.3mm. Vias are 0.7/0.4 and there’s only a bottom ground pour. I’ve removed all the copper near the ESP8266.
If you’ve got a moment, could you take a look here ?
The bottom pour is still a bit of a mess but I just can’t squeeze much more in.
Any advice is appreciated :slight_smile:


Without seeing the ‘back’ this is the only thing I can see right away I would do:

Some more observations:

  • be careful with vias close or in pads, they can suck the solder away and cause trouble. Place them with a piece of track from the pad, so soldermask is able to cover them completely (C2 via is good example, D2 cathode via is bad example)
  • remove the PTHs in that ESP footprint… if you’re unlucky they will cause ‘cold’ solder joints you won’t be bale to see (sucking solder into the PTHs)
  • if you turn Q1 90deg Left, you can optimize routing there

IMHO still a lot of stuff that could be done better, but you’ll get there at some point, don’t worry :wink:


Avoid tracks running close behind PQFP pads like the one from pin 29 close to 26 to 28, just asking for a bridge.
Also remember that flux residue is often highly conductive. Cleaning boards properly, when so many of the traditional solvents are banned, means soapy water in an ultrasonic bath


Thanks again, really good feedback.
If you have a look at the files, one of them is a multipage PDF which shows the underside of the board…is that what you were referring to ?


thanks, will fix…on the cleaning front, why not IPA ?


I’m pretty sure your component placement could be optimized by a lot. But I don’t have the time nor really want to do it for you, so yeah… you’ll learn by doing it.

Again, if you try to get better - start a new layout (empty), import the netlist and then start by grouping the components together. You can avoid a lot of vias and criss-crossing of the board by doing that and probably keep most of the routing on the top.

Also, I just noted that you didn’t put the buffer capacitors close to the IC power pins, but some unimportant resistor instead…

As I said, if you want to get better at this, start a blank layout file, import the netlist and group the devices together by function and where they need to be. Then you can arrange those groups on the board and work on optimizing the overall layout… atmo it’s more like a dogs breakfast :wink:


Most schematics I do can be broken into sections. I use numbering to help identify them. Everything in the power section might be in the 0-9 range. c1, c2, c3, r1, u1. My last one had two opamps so every thing became a 50 or 60 number. This help keep things simple when you lay it out. Also, you can lay it out section by section outside the border of the paper and then move them in as a group for layout.