Say you have a board where only one of two chips will be actually installed, but could be either one. But this means that in the schematic two output pins will be on the same net and ERC will complain.
So, live with the ERC warnings for those two chips? Or is there a special symbol like a 0 ohm jumper that takes no room that you can put in series with both outputs and avoids the warning?
A net tie (do a forum search, there are quite many threads about it). However, it takes some space. In the future (in 6.0) it should be possible to use net ties which don’t use space or use less space.
Depending on the nature of the “parallelism” between the parts, you may be able to create a custom footprint with pads for both components. Several years ago (when I was working with another layout program, before KiCAD) a project called for an IC (dual opamp) that could be either an 8-DIP through-hole package, or an SOIC-8 SMT package. I managed to create a footprint with pads for both packages, so either variety could be installed. I have also seen a similar approach used for electrolytic capacitors, where the lead spacing depends on which manufacturer supplied the capacitor.
Dale
I’m kind of proud of this one…
Yeah, that’s the idea! One footprint that can accommodate either of two different components.
Dale
A little bit of a side note, but can you not waive ERCs & DRCs in KiCAD? It would be nice to still see errors and warnings pop up but have some kind of flag with a comment section that indicates they check has been waived.
This topic was automatically closed 90 days after the last reply. New replies are no longer allowed.