Is that bought software, or subscription based? Have you thought about what 2 or 3 years of subscription to the current software costs for all the people in your company? For KiCad, you can get a lot of personal attention for that sort of money. You can contact https://www.kipro-pcb.com/ to discuss options for sponsoring priority development.
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It’s bought, otherwise I think the choice of switching would’ve been made earlier.
Pretty sure I’ve talked to my boss about kipro, definitely a good program, hoping I can convince them some day.
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But the rats nest parts like the bypass caps, get intermingled. If they are clustered by sheet, I can just highlight the cluster and move to the area of the board that I want them to end up, That means I’m not going through the laid out PCB and manually moving caps from one side of the laid out board to the other - because I’d put C1 with U13, instead of U1 etc.
Remember the parts had already been organized by groupings on the sheets. If it requires clicking and marking individual parts on large “super rats nest” before moving - that’s a lot of steps.
I came here to ask about EMI/EMC, field coupling and so on. It’s one of the few things that Altium has that I could really use (and I’m sure anyone who cares about signal integrity should – and by anyone, I really mean anyone).
It’s really tough to model parasitics accurately on paper and a “heat map” showing (for instance) coupling could be a killer feature. I can work them on with paper, calculator and Saturn PCB tools but that’s a huge amount for every single trace.
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That makes it simple then:
- Open both schematic and PCB via the project manager.
- Draw a nice (or an ugly) box around the capacitors on the schematic.
- Right click on the PCB editor, and select Pack and Move Footprints [P] from the context menu.
Alternatively (my preferred method) Activate the PCB editor by hovering the mouse over it and then rotate the scroll wheel (one click or back and forth). This transfers focus to the PCB editor with minimal side effects (Can also be done with Keyboard shortcuts). And once the PCB editor has focus, press P to Pack and Move.
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I’m coming from Orcad/PADS. While it’s certainly not easy/reliable, there’s a clumsy path to import both Orcad schematics and PADS layout into KiCad that involves a trip through EasyEDA. In case you didn’t know. I did most of my migrating the old-fashion way (pretty much redo it all manually) before I found out the path through EasyEDA.
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I tried that, and wow - it is not at all obvious.
I don’t believe that’s in any of the help or online files…
Yup, I’ve tried it, it kinda works but it’s definitely a very roundabout way of doing it.
I also don’t like how it keeps easyeda symbols and fonts.
Also I’m wondering about the safety aspect of pushing company-made cards to the Chinese cloud.
Agreed. There’s a ton to clean up with lots of oddities, but it still would’ve save me many hours and days had I known about that path when I started with KiCad. I don’t think that path was available until somewhat recently though. I started with V6/V7 era. Most every EDA ‘translator’ I’ve ever used was far from ideal, if it yielded at all.
I used the ‘Pro Full Offline’ version. I just unplugged my internet and it launched and loaded designs I had previously translated just fine without any cloud connection. I don’t think it did anything cloud wise when I first imported my OrCad schematics and PADS layouts other than the registration process, but perhaps it grabbed my designs behind my back. If they did steal and use any of my stuff, It would more likely set someone back 10 yrs rather than advance them.
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you can do a similar conversion (OrCAD/PADS) using Altium, i did it with a 1 week eval, no need to send proprietary designs around. Lot of clenup work is expected.
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Good to know. Thanks. When I first started with Kicad, I hate to admit how much time I spent trying paths like EDIF files and the like that never yielded anything more than a halfway jumbled mess for me. I’m far enough down the KeyCad path now that I already have most of my legacy ‘meat’ in KiCad format now. I haven’t launched OrCad or PADS for months now, but that could change tomorrow if my boss asks me- “Remember that design you did 8 yrs ago?, well Marketing would like . . .”
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Oh there’s an offline version? Yeah that would solve one of the major issues.
Lol!!!
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Same. I’ve made some hilarious boo-boos. So good luck to anyone who wants to sort through those messes. I’m leaving them around so I can explain to my community the rakes I stood on and how to avoid them.
A post was split to a new topic: Cannot assign multiple nets to the same net class? because it was a new question.
Hello:
I think that auto members to bus / hierarchical connections is essential to speed up the schematics.
When work on big schematic 9 or 10 pages, with buses of 25 or 40 signals is tedious add one by one. Only to remember: the “Alias Bus” manager bock the schematic, you cannot keep the schematic and manager at same time, so you need write in a paper the signal list.
Best Regards for everyone
Or put a quick screenshot on the second screen 
i understand, but i think that the feature request point to simplify the job. In altium i create two harness called “Inputs” on two sheet, put “input1” in both pages and the net is connected.
I would say the way “Custom Rules” are working should be revisited.
For instance, I would treat all of the rules from top to bottm of the list, with the most restrictive having precedence over a less restrictive.
At least, if a constraint in a rule is slightly different from another constraint with the same condition in another rule, it should be treated as a different rule.
Example:
(rule DIFF-SKEW
(condition "A.hasNetclass('BUS')")
(constraint skew (max 1mil))
)
(rule DIFF-SKEW
(condition "A.hasNetclass('BUS')")
(constraint skew (max 1mil) (within_diff_pairs))
)
The previous rules adress two totally different situations.
One is to tune a bus, different diff pairs in a Net Class, while the other is to tune the wires of individual diff pairs in that same set of net in a Net Class.
Does it make sense ?
Clear this bug: