What does the DRC's refill zones do and why does it do it?


I’m new to Kicad and just ran my first DRC on my first PCB circuit. The DRC said that my zones were out of date and that asked me to either refill or continue without refill.

Continuing with refill makes wide clearance cutouts around all my vias, this also supposedly breaks some connections to the internal planes where I have 3.3 plane and a GND plane. The broken connections are routed with vias to their respective internal layers and do not look broken to me.

Continuing without refill creates a normal looking pcb without big clearance cutouts around the vias, it also results in no broken connections.

My questions are, why does DRC ask me to refill? What does refilling do? Can I continue without refilling?

DRC without refill:

DRC with refill (notice cutouts around via):

DRC with refill (an example of a broken connection)

Any help would be greatly appreciated.

Refilling from the DRC is just a safety measure in case you haven’t refilled before opening the dialog. Actually you must always refill because that’s how the zones and KiCad work. It’s a very basic thing, as basic as tracks/traces. Each zone usually belongs to a net and so do vias and tracks as well as footprint pads. When the zone is refilled it’s connected to the items of the same net and it avoids items from other nets, obeying the effectual clearances.

If refilling causes troubles it just reveals that something is wrong in your design. For example maybe you have vias which don’t belong to any net. It’s difficult to say because you don’t show the same detail with and without refill in your screenshots and you don’t tell what detail is wrong, and the zoomed out view is too small for details.


Hmm ok. I have uploaded the PCB if anyone would care to look, probably better than uploading pictures.

DLDroot(STM)(1).kicad_pcb (1.2 MB)

It’s good you ask this.
I had a look at your Board, and apparently you have not re-calculated the zone clearances for a long time on this PCB.

This screenshot is from KiCad’s own 3D viewer [Alt + 3] and from the same general area as your screenshot. I’ve turned the inner layers off. To be able to look through the PCB I’ve also turned off: 3D-viewer / Preferences / Display Options / [ ] Show board body and the Solder Mask, as that usually also covers almost all of the PCB. Look at how long the via’s are:

Then the same screenshot, but with the “GND.Cu” layer turned on:

(Almost?) All your via’s are shorted to the GND.Cu Layer. (And the same for your PWR.CU layer, and both GND.Cu and PWR.Cu are therefore also shorted to each other through all these via’s.

Then I ran DRC without re-calculating the zones, and I only get two warnings for overlapping courtyards.
I am actually quite surprised that DRC does not complain about all those via’s in your signal lines shorting both your 3V3 power plane and to GND. Apparently it trusts blindly on the zones being re-calculated.

Now again a screenshot form the same area, but after pressing [B] for re-calculating the zone boundaries:

This re-filling of the zones re-calculates the internal geometry of the zones to make sure that a clearance is kept from all via’s. To do that it does poke holes in your GND and PWR zones, but that has to be done to get to the other side of the board in those locations.

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This is how the DRC works, at least in 5.x: zones don’t need to be DRC-checked, because the act of filling zones ensures no violations. This is a big performance optimization, but it also means that you need to keep your zones filled, which is why the warning message exists :slight_smile:


Thanks again Paul, so if I understand this correctly…;

"My questions are, why does DRC ask me to refill?"

Changes are made to the different layers in a PCB when routing tracks,vias,etc. - DRC asks me to refill zones in order to take the various clearances associated with the routing (i.e tracks, vias, etc.) into account.

*** What does refilling do? ***

What you said and - " This re-filling of the zones re-calculates the internal geometry of the zones to make sure that a clearance is kept from all via’s."

Can I continue without refilling?"

No, without clearances every single via would result in unwanted shorts throughout all levels of the board.

Now I am wondering, why the refilling results in the 9 unconnected items…?

Is this because the clearance/non-filled areas around the vias block the placing of tracks?

I’ve moved some via’s around a bit, and all unconnected items disappeared, so they were because of via’s too close together and the clearance of one via overlapped with a via that should not have clearance. So it’s easy to fix.

Some other remarks. Your PCB looks quite good, but I have not looked too deep into it (I’m also not an expert on this).
There are a few things I would change though. (Maybe someone with more knowledge can chime in too)
I would swap the PWR.Cu and GND.Cu layer. Reason is you get the GND closer to all footprints, which reduces EMI.
I’ve also gotten into a habit myself of giving each GND pin 2 via’s, one on each side of the pad. I’m not sure if this is important though. The connection between the pad and the IC itself is already much longer then the via. For the decoupling capacitor it does help to bet better performance.

I’m a bit surprised by the routing of +3.3VADC.
This track cuts both trough the GND plane and through PWR.CU.
I assume the 4C16M16SA is some memory chip with lots of relatively high sped traffick? You really do not want to cut the GND plane below all those signal wires. If you really want to keep +3V3VADC on internal layers for some reason, then route it around those signal lines.

This is not a board review. Just some remarks I noticed while toying around with your design. It’s quite late here already and time to go to bed now.

My first impression: do those clearences in your zones are not too big. Just relatively to vias seems very big (I didn’t checked anything - just looked at pictures in thread).
I am designing 2 layer PCBs with all bottom being GND. During placement I am used to (from Protel) to hide GND connection to see only connections I will have to route. As KiCad (5.1.9) don’t allows to hide selected net my way around is to place GND zone at top and press ‘B’ hotkey (refilling zones) very often.

If you go to Pcbnew / Inspect / Design rules Checker / Unconnected Items (9) and then click on any of the messages, Pcbnew pans to the location that it thinks has something to do with that message.

I usually take the center of pads and vias as a reference for when it is connected to a track or zone. Sometimes KiCad also accepts connections if the attachment point of a pad or center of a via is not precisely reached, but those are a minority.

The first unconnected is:

The cutout in the zone for the SD-D15 via is so big that the center of GND via next to it is not reaching the zone anymore. The others are also that obvious and can be fixed by just moving the via’s around a bit.

As Piotr already wrote, the clearance for the zones is set to a quite big value. You can change the clearance for a zone by modifying the zone properties. In the screenshot below, I already changed the clearance of the +3V3 net from the (default?) 0.508mm to 0.3mm, but for the GND zone it’s still 0.508mm. You can see the huge difference in size around the via’s.

Rows of via’s making big gaps in power planes is not very good. It’s better to drag the via’s in the screenshot apart a bit, so each via has it’s own small hole and currents can flow inbetween the via’s through the GND plane.

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Thank you again Paul and also Piotr!

Yes it was the default value of 0.508 mm that the clearance was set too. I’ll have to read about the other parameters in the “Copper Zone Properties” tab, assumed that the default values were adequate and did not really bother to research what they entail…

I have now set the the clearance to 0.3 mm and exported those settings to all the other layers. This resolved the disconnects. I will now move vias to ensure minimum GND/PWR splitting to ensure better EMI/noise performance.

@paulvdh, you mentioned that I should switch the PWR and GND layer, can this be done without needing to reroute the entire board? My guess is no.

Thank you very much for your help! :pray:

You guessed wrong.

My first idea was to temporarily set the board to 6 layers, move GND to a spare layer, move +3V3 to the old GND and then move GND again and return to a 4 layer PCB, but even that is not needed.

You can simply: Pcbnew / Edit / Swap Layers

Assuming there are no Swap Layers function.
What wrong in deleting both zones and adding the new (not using extra layers). Will something be destroyed during that process?
Deleting two zones and defining them once more is enough simple to not call it 'to reroute entire board".

If the only things to be swapped are 2 zones (one on each layer), you can also just edit the zone properties for those two zones and pick different layers for them. Swap Layers is more useful if you have lots of zones on the layers, or a mix of zones and tracks.

I’m glad you guys are still thinking clearly.

Looks like that last part was a combination of OP posting the first thing that came to mind about this topic, and me responding directly to the question on auto-pilot without taking the “bigger picture” into consideration.

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