Clearance basically IS crucial. They must not overlap any copper. Clearances are set to meet the manufacturer’s capabilities, which are typically something around 6mil for prototype boards. But I wouldn’t push the envelope. Most of my boards are 10/10 mil. Depends on board complexity, but for hobbyist purposes you rarely need finer. That can be manufactured even by the shabbiest of board houses 
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Thank you for the detailed insight, though I don’t clearly understand and am a bit intimidated by these finer measurements you mentioned (6mil, 10/10mil etc.) I get the idea that from a hobbyist perspective this should not create much problems to get the PCB fabricated.
Nothing intimidating here. Just go to JLCPCB, Pcbway, Elecrow, OSHPark and a zilllion others and check their capabilities to get a feeling.
Yes and no. There are a few constraints you have to honor. Maximum board size for prototype is 100x100mm typically. Larger formats cost. A couple of bucks for one manufacturer, a ton for others. Same for minimum drill diameter. There can be significant differences between the manufacturers.
It is good practice to get a feeling for that before you start your board to avoid changing things down the line for manufacturing reasons.
Feel free to turn to the forum if you have questions, no matter how many. And for sure you can post your (first) board for review here if you so choose.
Most important: relax and enjoy the journey.
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The clearance line means that “this copper item requires this much empty (copperless) space around it”. Therefore the lines themselves can overlap but they must not overlap with copper. The manufacturer tells in their “capabilities” how much each kind of copper item requires space around it, sometimes also more accurate as a matrix like “between pad and track”, “between pad and pad” etc. Often they are difficult to interpret at least for a beginner. Therefore you should find a good maximum value of those of the recommendations of the manufacturer, then add some amount to it. In general 0.2mm or 0.25mm is a good default for minimum clearances which all manufacturers can do. The minimum track width is often the same amount.
You can’t of course change the actual clearance between pads of a SMD component because the footprint must adhere closely to the datasheet recommendation, and the smaller the pads/clearances, the better manufacturer you may need. But if you don’t use very small components you don’t have to care about that.
There’s a way in KiCad to set very complicated and fine grained clearance and other rules in a text form, but normally it’s enough to use Board Setup → Design Rules → Constraints for minimum values and then set Clearance, Track width, Via size and Via hole in Net Classes for each net class. And if you need to ask what are net classes, you probably only need the Default one. 
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Also, these clearance lines are only for you during layout. They will not show up in the Gerber files, so no need to worry about the board house seeing them and getting confused. They have their own tools to find clearance violations in the submitted Gerber files while prepping for manufacturing.
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BTW Wouldn’t it be a good decision to place this option in the objects sidebar:
It’s a bit burried within the preferences.
The presets would have effect on this setting too.
(The current v6.99 has some new cool settings at the objects sidebar but this wasn’t included.)
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Probably intimidated because you were mentioning of measurement standard I am not familiar with and the thought that so many tiny variables are involved here that you have to be aware of that can potentially make or break my PCB designs. So initially I didn’t clearly understand what you were saying now after reading all your posts again and converting the measurements to SI units things are getting clearer for me.
What about it, do you mean that if I keep the drill diameter and the number of different sized holes used in the PCB to a minimum that can may potentially reduce cost?
Thank you for the invite and helping attitude all of you are showing here, its really appreciated and I did learn a lot from here. I will try to make the best use of this forum in my new journey, which I kept deferring for quite too long. And the the thought for posting my ‘first’ PCB (I had tried few times before and abandoned.) for review surely crossed my mind couple of times but the thought of feeling of embarrassment to show out my newbie mistakes to a larger knowledgeable audience and my self doubts about use of English language properly to communicate my thoughts were keeping me away from making such a post. I will try to be less harsh on myself and ask my doubts on PCB design and KiCad more freely here.
Thank you it’s really clear now.
Thank you for those insights. Now I am into the learning mode of finding out best track width for each type of connections (nets) between component, I know it depends mostly on basic electronic principles but do you have any general suggestions.
Also might cost more as the SMD component sizes go down? I am indeed trying to use some SMD components in my first board which I can hand-solder.
Thank you. Do you suggest any minimum values for differential pair tracks and copper to edge clearance here.
Thank you for the reassurance, appreciate it.
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No. Formats larger than 100x100 and drill diameters below 0.3mm infer additional fees. Number of different drill sizes does not matter.
I’m talking about JLCPCB here and their 5 bucks prototype boards. PCBway is similar.
Btw, I’m no JLCPCB agent 
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As I already wrote: go to the board houses and check their capabilities. 0.3 - 0.4mm for copper-to-edge are quite common.
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Btw, those depend on the desired impedance. Has nothing to do with manufacturers or pricing.
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Rather than feeling embarrassed, treat the reviews as mental exercises for we “not so youthful” forum dwellers… Your contributions will help in the prevention of our brains turning to senile mush. 
The same applies for the English Second Language problems. 
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For many, many years I was using 10 mils / 10 mils (track/clearance).
Then I changed it to 10/8 (but allowing myself for 8 mils tracks if needed). But for zone fills I still used 10 mils clearance.
When moved to KiCad I changed from (standard in PCB technology) mils to mm.
Now 10/8 → 0.25/0.2 (but allowing myself for 0.2 mm tracks if needed). And, not surprising, zone clearance 0.25 mm.
My 2 layer PCBs are designed that way, that whole bottom side is GND zone. So I don’t have other vias then GND. I use as typical via hole 0.5mm as I treat it as power connection and not signal. For power pads (under ICs) i use via hole 0.3mm. For via stitching of big GND islands at top with GND at bottom I use via hole 0.7mm, but I consider to replace it with 0.5mm in future.
For VCC tracks I mainly use 1mm track, but sometimes up to 2mm.
An example of such designed PCB you can see here:
Hand-soldering SMD is even simpler than soldering THT. You need not to revert PCB all the time. 0603 is easy to solder provided you have right soldering iron.
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I use a small oven for modified pizzas with MCU temperature control.
I must say that it works perfectly after doing some test welds.
Cards with SMD components are fine.
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A geunine wooden fired oven?
Sorry guys, but I belive the discussion is misleading. One thing is the manufacturability, which should be no matter for industrial suppliers. Hand soldering requires a little bit more distance for the solder pads but the real reason is different.
You may have a look on the pcb calculator section of the KICAD suite. There you will find a rider for electrical distance. You will clearly see, that for different applications you will need different clearances to ensure the voltage hardness of your PCB. The larger the applied voltage, the larger the required clearance.
So if one device is designed for high voltage application, the clearance must be much higher than for low voltage operation, otherwise you can meet an impressive firework one time…
But from the given sample from straubm I doubt that this is the real reason for this different clearance…
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I don’t know how this would be misleading. Well, it could have been mentioned explicitly that we are talking about minimum requirements for manufacturability only, not from electrical standpoint, and you need to know more about electronics and clearances and copper width/thickness if you are going to design with high voltage, high power or high speed.
Thank you for the feedback.
Some simple questions:
- did you notice, that any PCM manufacturer was not able to process the standard footprints provided with KICAD?
Please tell me if your answer is different to “no”. - what are the cost driver of a PCB?
For me this are:
- Number of layers
- board size
- technology (line width, drill diameter)
-special items (buried vias, filled vias, …)
One of the most important thing at the beginning of a project is to select the technology you intend to produce the board. By maintaining the technology design rules the manufacturability is ensured. The standard design rules implemented in KICAD are such that nearly every PCB manufacurer can handle them in a cost effective process. There design rules are applicable to a standard design for low voltage operation. Enhanced technologies allows smaller pitches (line width and space) even into the range of the IPC limits and below. So the discussion above does not really deal with manufacturability but with cost effective way to
make a PCB.
- Where is the clearance used?
First of all, not by the manufacturer. When the manufacturer gets your gerber data, the first thing they do is to run a DRC (design rule check) with the limits of the ordered technology. If this is OK, fine.
They don’t care about distance or overlap of the clearance. That is an issue of the DRC in KICAD. So for the setting of the clearance two limits needs to be respected: First the design rules of the manufacturer for your selected technology, second for the operating voltage of your board (or parts of the board). The DRC will show violations of this distance, which means, that the voltage hardness is not given at that point or the technology limits are not met. The latter can be handled by redesign of change of technology. The first must be carefully redesigned (no real alternative). The mentioned differential tracks are one more sophisticated setting since you need to respect the material and layer thickness of your PCB process.
As I mentioned, with the standard settings of the KICAD suite you are on the safe side for the manufacturability for most PCB manufacturer. But if there are some deviations in clearance you need to think about electrical issues, which may have a much sever impact than manufacturability…
And this is at least the answer of the initial question: These lines are indicating the minimal distances to neighbour areas. They are indicating the design rules for the selected technology in combination with electrical requirements and can be adjusted for each project in the way it was shown above.
These lines can overlap; a design rule violation is given by the explanation above when this clearing line is overlapping any neighbour metallization (copper line, filled area, pad, via…).
These lines are used by the DRC to ensure a proper layout which fulfills all technological and electrical limitations for your project.
They are used by the auto-router too to have a proper distance to the pads, which can also block routings through two neighbour pads. By this mechanism DRC errors are mostly excluded for drawn lines.
I suppose you mean “PCB”. KiCad has footprints for some very small components, or components which many small pads, which may be too difficult for some low end manufacturers because the space between pads is so small. I don’t know if this actually is the case with most footprint/manufacturer combinations, but it’s not ruled out. On the other hand at least some manufacturers who give a certain minimum requirement may silently accept a footprint which has smaller clearances between its pads. All I can say for sure is “it depends”.
Sorry for the typo.
I personally didn’t found too much low end manufacturer which are not capable to process the default settings in KICAD for a new project: line width: 0.25 mm, spacing: 0.2 mm. This is usually the bread and butter process. This spacing is derived from the default net class and is by default applied on pads too. Using this default net class PCBs for application voltages up to 24V can be designed without violating the IPC guideline.
And yes, there are some high density packages in the footprint library which are violating these default sizes, which will be highlighted by the DRC. With this information you can decide how to continue: use a different/larger package, check/adjust the DRC limits for your envisaged manufacturer technology or switch to an improved (and mostly more expensive) technology node. But I assume, that is no typical beginners issue.
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