I am trying to use 01005-packaged components (imperial size; the metric equivalent is 0402). The footprints are straight out of KiCAD’s git repo. When I run a preliminary DRC check, I get errors like this:
ErrType(19): Pad near pad
@ (5.5689 in,3.7503 in): Pad 2 on B.Cu, Non-copper of C208
@ (5.5689 in,3.7670 in): Pad 1 on B.Cu, Non-copper of C208
This seems to be a systematic error relating to pads placement on the 01005-packaged components. I also have trouble understanding what “Non-copper” means in this case. I thought DRC only cared about copper layers, no?
Some board houses have separate trace-to-trace, trace-to-pad and pad-to-pad requirements. I don’t think KiCAD makes this distinction. So, I have declared an absolute minimum track width of 3.5mils (0.0035 inches) from the “Design Rules” menu button (“Design Rules” menu button → “Design Rules” →"Global Design Rules"). I also entered 0.0035 inches minimum track width in the DRC window. I am not sure if the last two track width settings also imply that the copper-to-copper spacing will be the same.
Measuring the copper-to-copper spacing of the 01005 pads on the grid, the are around 0.007 inches, so there should be no problem. What does that cryptic “Non copper” mean?
PS. Sure 01005 is a very small package, but KiCAD can do it! 01005 imperial is one package size smaller than 0201 imperial (0603 metric, Ithink). There is a package size yet smaller than 01005 imperial. I am also using buried vias, which KiCAD seems to handle well.
There is exactly 0.15mm of pad to pad clearance. So if your DRC settings require larger clearances for copper to copper then you might have found the reason for this problem. (conversion to imperial is left to the reader. Remember there could be rounding errors in this conversion!)
It was not the pads of the 01005s themselves. It was the nets they were connected to. Some of the nets in my design are power nets, for which I declared, through the net classes editor (“Design Rules” menu button → “Net Classes Editor” tab) 7.5mil trace thickness and (unnecessarily!) also 7.5mil clearance. Once I reduced the minimum clearance of the 7.5mil-thick traces, all DRC errors went away. I guess it was like forgetting to close a bracket in a C program, where the compiler gets confused and barfs several lines downstream, not where the omission occurred.
So, as long as KiCAD allows you (depending on what absolute minima you have declared) to enter a copper-to-copper spacing for a net, that is what the DRC uses.
Thanks to everybody who responded. I would mark this (non)issue as solved.