I want the filling to fill all the way next to the NPTH. I have co custom rule about NPTH, and all my clearance settings are set to 0 both for the zone and global:
This becomes even more confusing looking at the back layer which is filled differently (light blue above) which is filled differently?
Can anyone hint me on how to make the zone fill all the way to the NPTH. Actually, even better would be if the zone also filled the NPTH. That is the recommended way to have copper from the PCB vendor.
What I don’t understand is why you want a NPTH surrounded by copper. Why not just juse a plated hole? Plated holes are easy for PCB manufacturers because the process is already in place for making via’s (Although not in the same diameter).
@der.ule , It looks like you are using a regular via hole which I think is different.
@paulvdh , this is the way my PCB vendor wants it. I want npth-holes for various reasons and my vendor wants copper all the way until the hole edge.
I think this is a bug in 6.0.4. Great if someone can confirm. I did not have this problem in earlier versions of KiCAD.
I have attached an example demonstrating the problem:
The gap to the NPTH cannot be made smaller than 100 µm. I can make it larger by increasing the clearance setting, but not smaller. npth_bug.zip (269.5 KB)
But actually, because of a bug, I am not running v6.0.4, but a testing version (one or two weeks older than v6.0.4) and I assume therefore I do not see it.
Application: KiCad PCB Editor (64-bit)
Version: (6.0.4-53-gbf8c7d7697), release build
Libraries:
wxWidgets 3.1.5
libcurl/7.78.0-DEV Schannel zlib/1.2.11
Platform: Windows 10 (build 19043), 64-bit edition, 64 bit, Little endian, wxMSW
Build Info:
Date: Mar 24 2022 22:10:09
wxWidgets: 3.1.5 (wchar_t,wx containers)
Boost: 1.76.0
OCC: 7.6.0
Curl: 7.78.0-DEV
ngspice: 36
Compiler: Visual C++ 1928 without C++ ABI
Build settings:
KICAD_USE_OCC=ON
KICAD_SPICE=ON
Ok. Thanks. No matter what I change it to in my version of KiCAD I cannot get it below 0.1mm. I know it was set to something other than 0 in the example file. The point is that it does not help to set it to 0 in that file on my machine.
@mf_ibfeew , which version of KiCAD are you using? This is mine:
@mf_ibfeew you are totally right, I didn’t even notice
However I tried again (this time in the correct hole -.- ), the distance from the copper to the hole was set to 0.1mm I changed to 0mm and now it seems correct
I always find it encouraging when people attach a test project to a thread.
I’ve tried various things and KiCad tries to outsmart and ignore the settings I enter.
For example, I’ve added a “Mountinghole_Pad” to the schematic and attached it to the GND net, but NPTH footprints on the PCB do not accept a net name.
Setting the pad diameter to bigger then the hole diameter draws the pad as expected, but because a NPTH does not accept a net name, there is still a clearance.
I’ve tried to set the pad diameter smaller then the hole diameter, but the zone recognizes the hole is bigger then the pad and keeps a clearance from the hole.
Negative clearances are also not accepted.
The method suggested by mf_ibfeew also does not work properly
I can set that clearance to zero, and refil, and that does create a hole of the drill diameter (verified in the created Gerber files, but it only works because the clearance of the zone itself is also set to zero, and that is something that never works properly. The result is that the two connectors on the left are also shorted to the zone.
KiCad behaves quite weirdly for these NPTH.
If the pad is set to bigger then the hole size, the whole pad is drawn (also in the Gerbers)
If the pad is set to smaller then the hole size, the pad is not drawn at all (in the Gerber).
I think I consider it a bug that the pad of a NPTH does not accept a net name. If the pad just accepted a net name, then it can be attacked properly to the zone.
@ravn : I have to apologize, in fact I have also not the stock 6.0.4., but a later testing build ((6.0.4-159-g729cf7a39d)) from 26.4.2022. (like der.ule).
So try to download a current testing-version from Downloads | KiCad EDA. If you choose the *_lite.exe no settings+libraries will be overwritten - so very little risk to damage anything on your installation.
And what’s even better, 6.0.5 was tagged in the source code yesterday, so the final 6.0.5 which will be announced within about a week should be identical to this (unless some even newer bugfix has been introduced to the testing builds).
If I read this correctly, clearance should be 0 for both. Interestingly after running the clearance resolution tool and refilling the zones, the gap diapers! A bit opportunistic of KiCAD I must say
So, in both my projects (my live project and the minimal reproducing one submitted above), doing no change whatsoever except running the clearance resolution thingee corrects the filling issue.
This of course solved my problem, but it looks even more like a bug to me. Thanks everyone for engaging and helping out! @JeffYoung , let me know if you want me to file a bug report.
Well that’s a head-scratcher. Any chance you upgraded versions or anything since the last time you did a zone fill? (There were bugs in this area. I can’t remember if any of the fixes were as late as 6.0.5 though…)
Yes strange indeed.
I did not do anything to KiCAD, so this is running 6.0.4 built mars 18.
I reported another fill bug that you @JeffYoung helped out with regarding rounded traces. But I suspect this is unrelated.
