I’m creating gerber files for two of my layouts today. I see a big warning in that dialog window that I cannot remember I have seen before. And I’m not aware that I broke anything. What am I supposed to do now? Can I ignore this? I uploaded one of the archives at JLCPCB and the preview looks fine.
The version is KiCad Pcbnew 5.1.9 on Windows 10.
This is somewhat controversial. Many manufacturers want to adjust the mask clearance themselves. In that case the clearance should be set to 0, i.e. the mask opening is identical to the copper pad. JLCPCB probably accepts your clearance value if it’s within their limits.
Unfortunately many manufacturers don’t communicate clearly what they want. They may give the clearance value but don’t tell if they want you to set it or leave it to zero and let them handle it.
So there’s nothing I can do, whereever I could do that after all? I don’t know where to find those settings so I could at least check them.
The setting is in: Pcbnew / File / Board Setup / Design Rules / Solder Mask/Paste / Solder mask clearance:
I set that to 0.2mm and then also got the warning.
Weird thing though, I have the buttons at the bottom in a different order:
Different widget libraries have their own order for standard buttons or they follow the platform conventions. GTK (Linux) has its own AFAI can remember, Windows and Mac have their own orders.
Okay, there was 0.05 mm set and after I changed it to 0 the warning went away. If that’s what KiCad recommends, I’ll happily follow it. I have no opinion on that.
Yes, different platforms come with different UI guidelines. While on Windows the basic rule is that the most important button comes first (in reading direction, that is), many other platforms use the reverse order. On mobile platforms the argumentation is that the most important button must be easily reachable with the right thumb while holding the device. I can’t really follow that and see no reason why that should be useful on desktop systems. So to me, everything except Windows just has it backwards and the first thing I find there is the least important action. But I can’t change that.
While the warning might look concerning if you aren’t expecting it, I see it more of a warning to double check to see what your manufacturer wants. KiCad itself can’t know that.
That reminder, however, does not appear if you’ve set those values to 0, regardless of whether that’s something the manufacturer wants.
Does anyone know of any fabricator that does not accept 0 clearance masks?
To me it seems the trend towards manufacturer specified mask handling is rather recent (last few years or so) and started with the cheaper fabs. It might be that they want to have the freedom to send an order to any of their partner facilities that currently has free capacity. The old standard where the designer specified the clearance meant that they would have needed to publish their worst specs to be able to do that. Now you the designer never see the specs and just hope that you get what you want.
I personally continue to send fully specified gerbers including mask setup as i want it (to the manufacturers specs of course). And at least the fab i use never gave back feedback that this would be unexpected to them (but they are a rather small fab in europe, so maybe they are outdated with their workflow).
Also consider that if you do not set the clearance and min width in the design tool how would you know that there is enough space between pads to get mask in there. (How often were you surprised that the gerber mask differs from what pcbnew shows. Now imagine the same happens with the 0 clearance specified workflow. But now instead of you being surprised when looking at the gerbers you have this realization when you get your order delivered.)
To be honest i am not really a fan of the warning that got introduced here (and i seem to remember i gave feedback regarding this quite some time ago). I fear this was an overreaction from the dev team about a trend set by certain fabs.
The mask needs a given clearance to copper, say a, a is the registration error in fabrication. (And different ones to NPTH, profile etc but let us stick to copper.) It also needs a minimum mask to mask, or web, say b. Whether that mask is possible or not is entirely determined by the copper. The pad to trace/pour clearance must be a. The pad to pad clearance must be 2*a+b. If these are met, the mask can be made. That is why there are seperate pad clearances, if it where only for etching, only a copper to copper clearance would be specified, etching does not know whether something is a pad.
IMHO the KiCad DRC’s must focus on the copper, and must do that very well. If the copper is OK, the mask can be made, and the fabricator can easily do that. As long as the KiCad copper DRC is not 100% perfect, I would not bother about the mask. The fabricator can handle the mask. He cannot handle copper layout errors.
Some of the PCB “fabs” are actually agents for a pool of (usually China) fabs.
This means that it may be the agent adjusting the clearance
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