Want a Bundle of Wire Feature over Bus

[BrendaEM]

For me, the current bus functionality in Kicad is useless. I want human-named signals on both ends of the bus. For me, I don’t really care what the bus is named.

The automatic numbering lower ports in the editor is useful, but the actual bus functionality is pointlessly restrictive.

Adding a Just-A-Bunch-Of-Wires or signals would be a lot better than what we have in Kicad.

Yes, there are times that you have sequentially named ports, such as a parallel connections, but Kicad overlooks the existence of cables, such as a CanBus for a car.

The idea that the bus numbering rules-checking comparing the bus with it’s contents is silly, as human-readable endpoint connections are more important than a limiting threadbare scheme to compare the idea of the bus against its contents.

Yes, I want the ability to name the bus anything I want–as long as the endpoints connect.

In my project, I need to connect 6 connectors to 5 chips, and what misery it is. If I use indevidual wires, it becomes a mess, like this:

There are many other applications where, say you might have a connector with various named signals that go from here-to-there, and we have no good way to present such an idea.

It doesn’t matter what other programs do. There is not reason why Kicad should live in the shadow of closed-source software.

Thank you for your consideration,
–Brenda

[retiredfeline]

I think what you are describing is the existing group bus feature in KiCad, documented here: Schematic Editor | 7.0 | English | Documentation | KiCad

To quote the relevant passage:

A group bus is a collection of one or more signals and/or vector buses. Group buses can be used to bundle together related signals even when they have different names. Group buses use a special label syntax:

<OPTIONAL_NAME>{SIGNAL1 SIGNAL2 SIGNAL3}

The members of the group are listed inside curly braces ({}) separated by space characters. An optional name for the group goes before the opening curly brace. If the group bus is unnamed, the resulting nets on the PCB will just be the signal names inside the group. If the group bus has a name, the resulting nets will have the name as a prefix, with a period (.) separating the prefix from the signal name.

For example, the bus {SCL SDA} has two signal members, and in the netlist these signals will be SCL and SDA. The bus USB1{DP DM} will generate nets called USB1.DP and USB1.DM. For designs with larger buses that are repeated across several similar circuits, using this technique can save time.

Group buses can also contain vector buses. For example, the bus MEMORY{A[7..0] D[7..0] OE WE} contains both vector buses and plain signals, and will result in nets such as MEMORY.A7 and MEMORY.OE on the PCB.

Bus wires can be drawn and connected in the same manner as signal wires, including using junctions to create connections between crossing wires. Like signals, buses cannot have more than one name — if two conflicting labels are attached to the same bus, an ERC violation will be generated.

[baldengineer]

Here’s an example of a group bus.

Notice how this (orange) bus is named {Control} with the braces. You can see there are unrelated names going into the bus.

And later, you can see the signals exiting.

And here is how it is set up in the Schematic Setup Dialog:

It is a little cumbersome to set up, but it allows you to “bus” any signals you want together.

It works very nicely in a case like this, where most of the signals come from a connector and go to an ASIC. There is no need to draw the individual wires, and it is slightly clearer than just using net labels. (With multiple busses, custom colors really help too!)

Edit, if anyone is curious, this comes from a re-drawn Game Gear schematic.

[BrendaEM]

baldengineer, thank you for the reply. It does seem along the lines of what I want, but it’s functionality was never apparent. I posted a thread not totally dissimilar to this one, and no one seemed aware of it. It’s not like there is a group bus icon.

I have dozens of signals I want to include. In the real world, the only checking that needs to be done on this is the endpoints, that obviously must be connected.

So why all the needless complexity?
Why is there no icon for this?
What does the added complexity get the user?
As far as rules checking, what would doing a cut and paste job from one part of the interface–to the other get the user?
(Do you really type your email, twice : )
Which aspect of good user interface design is putting actual parts of the user interface layout and creation–in the document(schematic) setup dialog?

If properly implemented, nearly every bundle of wires, every “harness” in a car would use this functionality–yet in Kicad, it’s buried and marred by bad user interface design.

As long as Kicad could check a bus to see if it’s members are connected and uniquely named within the bus, I at a loss the understand why, if properly implemented, why the functionality you demonstrated to me–should not replace the current bus scheme.

At the end of the day, even in a parallel bus usage, what really does the current bus legend numerical checking against its contents functionality get you–if it also prohibits you from denoting the bus in a human-readable way, such as: “high-order bits”, or “expansion-port” “to multiplexer-lines”?

[Bald Engineer, thank for the link. I am a big fan of the creation and dissemination of information such as schematics for older computers, games, consoles and devices. Information such you create helps people fix their stuff, and keep it out the the landfills. I watch a lot of retro-computing channels on youtube, such as Adrian’s digital basement, Jerry Walker, Usagi’s, Curious Mark, and Noah’s Retro Lab, as well as the NitrOS9 forum I am on, and people are always very appreciative any time there is a schematic available. Thank you for your efforts.]