I’m making a board with TI’s AFE4490 chip and I’m currently working out how to make the appropriate footprint for it, which is QFN-40 with 0.5mm pitch.
One option that I found was to use the existing “QFN-40-1EP_6x6mm_Pitch0.5mm” footprint in the “Housings_DFN_QFN” library. The library footprint was similar to the recommended footprint in the datasheet, but the dimensions were not as close as I’d like them to be. Has anyone tried using this footprint before? How did it work out?
Instead, I modified the existing footprint to follow the recommended footprint and solder paste patterns more closely. This is what I’ve come up with so far: (can’t upload the .kicad_mod file yet because i’m a new user)
Following the datasheet recommendations, I made the pin pads slightly longer and wider and made the exposed pad out of a 3x3 pad array with about 69% solder paste coverage. I also tried to implement the rounded inner parts of the pad by adding circular pads of the same net. Will these changes work? Do you think it will make much of a difference in assembly quality?
I noticed that the footprint provided by the library did not have soldermask between the pins in the 3D viewer, but mine does. I’m a bit new to making footprints. Are there any things to watch out for when putting soldermask between the small pitch pins, such as design rules?
I haven’t yet implemented thermal vias as suggested in the datasheet. I don’t expect to need them, but will likely put them in just in case. Any suggestions for a newbie on where to start for this task? Any suggestions for improving the footprint that I have so far?
Thanks for reading,
Maybe, maybe not. It depends on your manufacturing specs. Only you know what those are. To find out, you need to make a batch and monitor the quality.
Certainly, all fab houses have a minimum width for solder mask, frequently that means there is no mask between fine pitch pins. In practice, it doesn’t matter much, solder still sticks much better to copper than it does to bare FR4.
Yes, don’t get too hung up on paper specifications. The footprints in the datasheets are more like “serving suggestions”, they are one example that has a good chance of working in typical scenarios. In all cases you might need to adjust the specs according to your own manufacturing specs. But until you have some data from real manufacturing runs, there is no point in guessing.
There was some discussion of thermal vias in this thread I started about an HTSSOP footprint.
Also, I later contributed a script for generating QFN footprints to the kicad-footprint-generator repository. It supports thermal vias as an option. (It doesn’t support rounded pads, though.)
In addition, the KLC has some recommendations for thermal pads in rule 8.3 and for thermal vias in rule 7.7.
I wish I had read this when I first started.
Thank you for the info!
Since I’d like to have something functional on the first iteration, I’ll probably take the least-risk path and skip the thermal vias for now.
The lack of soldermask between pins in the default library footprint makes sense if most fab houses can’t put it there. I’ll have to keep the minimium soldermask width in mind when choosing fab houses and adjust my footprint accordingly.
Under the “Dimensions” menu there is a drop down of “Pads to Mask Clearance”.
An inch setting of “0.004” does not seem unreasonable for modern fab houses.
Use this info at your own risk.
@rgmarosi as you have discovered no two manufacturers can agree on what is required for a particular “standard” footprint.
The KiCad libraries have provision for this. In addition to the ‘generic’ footprints there is provision for parts of the format
You can see plenty of examples of this here.
My soldermask clearance is currently set to about 3 mil. I think i can still get away with 4 mil. Depends on which fab house I end up using.
@SchrodingersGat “Texas_PVQFN-N40_ThermalVias” in the library you linked closely matches the packaging of the part I’m designing the board around. That library footprint has dimensions closer to what’s recommended. It has a rather small, non-square thermal pad, but it comes with the option for thermal vias. Don’t know why I didn’t see it earlier. Thanks!
I’m no expert, but I’ve done a similar thing for the MAX2016 part. I did the Via’s at the PCB level (Net=GND), not the at the component level.
In the footprint, are the thermal vias tied to GND? I believe they will need to be tied to GNS when you do the board. It may take several attempts to get this right and I’m interested in how this turns out. You’ll have to look at the Gerber files to see the final result.
The thermal vias are given the same pin number as the exposed pad. This is usually one more than the total number of pins. So, for a 40-pin package, the exposed pad and thermal vias are all given pin number 41. (Therefore, the schematic symbol needs to have a pin 41, which will be tied to ground in the schematic.)
I have one fab house that takes whatever I give them without complaint and makes good working boards, and another that busts my chops about every damn footprint being ever-so-slightly different from the manufacturer’s data sheet.