Paste for HTSSOP thermal pad


#1

I have a beginner question about the HTSSOP footprints. The thermal pad has exposed copper, but no paste. For example, here is the footprint for HTSSOP-28_4.4x9.7mm_Pitch0.65mm_ThermalPad:

Am I supposed to create a separate footprint with a square on the F.Paste layer, and then lay it on top of this footprint? Or is there some other way to handle the paste? Or am I missing something? Thanks!


VQFN-40 footprint critique
#2

This footprint is quite strange. It seems the thermal pad is build with copper on top and bottom. (By using multiple square through hole pads.)
You might want to look at this footprint to see how it is done correctly. https://github.com/KiCad/Housings_DFN_QFN.pretty/blob/master/QFN-16-1EP_3x3mm_Pitch0.5mm_ThermalVias.kicad_mod

Normally the paste layer should be broken up into multiple smaller squares. (As is done in the qfn footprint i linked.)
Example for an application that gives details on this (yes it is for a qfn package but something similar will apply to your part as well)

A better more detailed application note (the interesting part is on page 5 and page 6)


Edit: Sadly this link seems to be dead. I will try to find another source for my claim.

It is a good practice to minimize voids within the exposed pad interconnection, so the design of the exposed pad stencil is crucial. The proposed stencil design enables out gassing of the solder paste during reflow and also regulates the finished solder thickness. Typically, the stencil apertures are reduced such that the solder paste coverage is 50% to 70% of the exposed pad area.

If you place thermal vias place them at within the spaces where there is no paste. (Otherwise the paste might wick through the vias)

I would not place as many vias as there are now. Look at the datasheet of your component, i bet there is a suggestion by the manufacturer. If not, search for an application note.


#3

Somebody wasn’t thinking through the whole picture when he created this footprint. Or maybe he thought the fancy-shmancy computer tools with the slick graphics would do all the thinking, as well as the work, for him. No matter . . . .

The “thermal pad” is actually an array of forty, through-hole pads. In KiCAD, through-hole pads do NOT receive solder paste by default. (That’s actually a very reasonable assumption.) However, in this case you want the through-hole pads to receive solder paste.

Open the footprint in the “Footprint Editor”. Select each of the “Pad 29” pads in turn, and edit it to add the “F.Paste” layer to the active layers.

Or, delete all of the “Pad 29” pads and re-create the entire array with pads that include the “F.Paste” layer.

It might be a good idea to check with your manufacturing guys on this footprint. They may not want the whole thermal pad covered with solder paste - that big blob of solder could cause the IC package to float up off the board, and prevent the pins from contacting their pads, resulting in dry solder joints. The manufacturing engineer may suggest that you put solder paste on less than the whole thermal pad - perhaps only the two central columns, or every other row, for example.

Dale


#4

Thanks for both of your comments!

This footprint appears to have both an SMD pad (to get the paste) and a through-hole pad (to get the hole) stacked on top of each other. But the paste in the SMD pad appears to be solid (there is no hole in it), so if I’m supposed to avoid getting paste in the holes, how does this avoid doing that?

Strangely, it seems to remove the .pdf extension when I follow the link, and it gives a 500 error. But if I manually add the .pdf extension in the URL bar, it seems to work.

The part I am looking at is TLC5947. (It’s an HTSSOP-32, which does not exist in the library, so I’ll have to create my own footprint anyway, but I was looking at the HTSSOP-28 footprint for guidance.)

On page 25, it shows their recommendation. It shows a 8x4 array of vias, and the paste is placed in a squarish area about 4.36x4.11 mm. (Although it says the exact area should depend on the stencil depth, which I guess I need to find out from my assembly house, which is probably going to be MacroFab.)

The datasheet doesn’t say anything about breaking up this square into smaller areas or avoiding the vias. The SLMA002 document linked from the datasheet does mention (on page 9) capping the vias with soldermask to prevent the paste from flowing in. How would I do that, exactly? It seems like I would need to make a circle of soldermask, and since the F.Mask layer says where to not put soldermask, it’s easy to create a circle of not-soldermask, but the opposite seems harder.

After I create my footprint, should I contribute it back to the KiCad library as an HTSSOP-32 footprint, or should I specifically call it a footprint for the TLC5947, since other HTSSOP-32 chips might have different requirements?


#5

On the other hand, the SLMA004 document also linked from the datasheet says, on page 1:

And the TLC5947 datasheet recommends that the vias be 0.33 mm, which is 13 mils. So it sounds like maybe I don’t need to worry about the paste going through the vias.

These documents conflict with each other to some extent, so it’s a bit confusing.


#6

Here is the footprint I made for HTSSOP-32.

I constructed it in the following way:

  • A big 5.2 x 11 SMT pad only on the copper layers, to create the copper pad shown in the figure on page 25 of the TLC5947 datasheet.

  • A smaller 4.11 x 4.36 SMT pad for the mask and paste, to create what the datasheet calls the “Solder Mask Defined Pad.” The datasheet gives different dimensions for this area, depending on the stencil thickness, which isn’t really possible to do in a general-purpose library.

  • A 4x8 array of THT pads, to create the thermal vias.

Unfortunately, the KLC scripts are very unhappy about this arrangement:

Checking footprint 'HTSSOP-32_6.1x11mm_Pitch0.65mm_ThermalPad':
  Violating Rule 8.3
    SMD pad layer requirements
    Some SMD pads have incorrect layer settings
     - Pad '33' missing layer 'Cu'
     - Pad '33' missing layer 'Paste'
     - Pad '33' missing layer 'Mask'
     - Pad '33' has extra layer '*.Cu'
  Violating Rule 9.4
    THT pad layer requirements
    Some THT pads have incorrect layer settings
     - Pad '33' missing layer '*.Mask'

(repeated a bunch of times)