VIPPO Design Guidelines

Anyone here have experience with Via-in-pad-plated-over (VIPPO)? I recently got the working gerbers back from NextPCB and they had changed my design pretty drastically with regard to the sizing of these vias and annular rings.

See below screenshot of comparison.

I’ve already commented about the misalignment (that didn’t exist in my design). But the pink layer shows the original size of my vias holes (0.25mm outer diameter / 0.15mm hole diameter). This leaves only 0.05 thickness on the annular ring, which I guess is quite prone to flake off. NextPCB’s drill file (blue) look to drill out the entire pad and leave no annular ring. Is this normal for VIPPO? Do you need any sort of annual ring remaining for the plating to work?

Although I have a WLP/BGA parts that make use of this, you can find one example here:

with a 0.4mm pitch on the WLP pads.

Maxim published this:

which states:

“Via in pad (VIP) is acceptable. The dimple at VIP can cause solder voiding at assembly. Small
voids at VIP do not significantly degrade the solder joint reliability. The user can assess the
acceptable via quality. Complete flat VIP can be achieved via capping although it is not required. It
is recommended to put VIP at the corner ball location to improve the PCB reliability.”

This is followed by recommended pad diameters (for 0.4mm pitch, this is 250um, thus why mine are 0.25mm). They don’t provide any recommendations on via or plating sizing.

Anyone have any experience with what works and with which manufacturers you have used in the past with reliable assembly for such layouts? I’m getting pretty frustrated by the slow reply/resolution speed from NextPCB (though I raved about them prior to their name change and likely buyout). Looking for alternatives.

Drilling out the whole pad will not result in a via, just a hole, so your instincts are correct there.
I don’t know anything about NextPcb, but in my experience the vias of via-in-pad should be defined in KiCad the same way as any other via, though normally with a slightly unique hole size to make it obvious which are via-in-pad. The difference is adding additional notes on the fab drawing to explain which vias need to be filled and capped (often an expensive process). If you don’t fill and just cap, I imagine you get the dimple described in the datasheet (which may or may not be acceptable for your assembly process).

Bookkeeping: This might be more properly filed under Projects and I’m assuming the design is done in KiCad (to clarify on-topic status).

@scandey thanks for your quick reply and confirming my suspicions. Yeah, it isn’t cheap. I’m paying something around 1k USD for 5 prototyping boards, but I would expect them do it right and quicker than they’ve done so far…so not very pleased this time around.

Not sure about moving it to Projects; that doesn’t seem on-topic to me, but if others agree, happy to comply. I was more interested in the footprint used by others for VIPPO layouts.

A couple of things com to mind, do Next PCB support 0.15 hole and with that size hole do you exceed the maximum aspect ratio?

For a 0.15 finshed via they probably want to drill at 0.25 in order to meet the IPC spec of -0um +80um tolerance

Hate to say this but you may need to consider microvias :frowning:

I frequently use 0.2 vias in 0.45 pads but even with that have to downgrade quality requirements from class 3 to class 2 in those regions

Yeah, they should. See screenshot below. Also I had the same parts produced by them in the past, but they didn’t send me a working gerber. As far as I’ve tested so far, they work too…so not sure if they did something different last time, or if the new team I’m working with there is just doing a bad job. (My previous contact there apparently left, and she was amazing, so there’s that too). Or maybe I’m just misunderstanding their working gerber file structure. They kept sending me screenshots of gerbers that weren’t included in the working gerbers…its a mess.

Maximum aspect ratio being hole diameter to board height? Looks like I did actually. Board thickness was spec’d at 1.6mm, though it really doesn’t matter much, so surprised they didn’t mention that either:

I think they other big thing they should be worried about is the annular ring width, as I’m obviously under their spec:

No worries there…just wish they’d request that I swap over to that rather than sneaking in these strange working gerbers modifications without even notifying me. (I just happened to notice them when doing a diff on their gerbers vs mine).

I’m not a full-time pro at this for long, can you fill me in as to what this means? Or link me to the class definitions or better yet a summary/comparison article? Maybe it doesn’t matter for me. (Likely doesn’t). These just for a small batch of research boards and not consumer facing (yet)

IPC 6011 defines 3 performance classes, given the cost of your boards I would guess class 2 would be appropiate and is generally the default unless cost is a primary driver
One of the differences for example is that in class 3 boards a via must have a complete annular ring >50um all round where as class 2 allows up to 90degrees breakout and class 3 allows 180degree breakout

@stair thanks for sharing. No, I don’t think we’re worried about meeting any such class standards at this point in development. Interesting to know though.

You are definitely at the very edge of what can be done for reasonable price without micro-vias. I did notice in your screenshots above that the 0.15mm finished drill is listed for <=1.2mm boards, which suggests that they may not be able to quite do 10:1 aspect ratio. Maybe they shouldn’t have allowed you to select 1.6mm board with 0.15mm drill? I’d definitely suggest calling/emailing with any notes you have from the first batch with similar design in case that helps clarify what is different this time. For whatever it is worth, a good manufacturing engineer (like perhaps the one who left) can make a huge difference on yielding good panels for edge cases like this… sometimes more an art than science.

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Free Via-in-Pad on 6-20 Layer PCBs with POFV pay attention to this technology, maybe it will suit you


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