I have been getting used to designing a PCB with KICAD which involves multiple layers design. Currently, I am designing a board with 4 layers, and I have a question regarding the power plane and VIAs.
I would like to power a 3V3 plan from a power source (battery) placed on the top surface, and I do acknowledge that I have to use a VIA to create a connection from the top surface to the inner power plane. My question is, is it fine that I just place a through-hole VIA from the top surface to the bottom surface, or only place a VIA from the top surface to the inner power plane? Will the through-hole VIA would function correctly (supply power to the 3V3 plane) as long as I assign a net label of 3V3 (my label for 3V3 pins) to the VIA?
Thank you and let me know if require additional information.
Welcome to the forum. I think you are asking about power PLANES.
Further I think you are asking about through vias in which the hole goes completely through the board (top to bottom) versus blind vias which are open to one side but not the other.
Both types are available if you are willing to spend a lot of money on the board. But if you do not need blind vias (such as to save space) then using only through hole vias is the way to go. Blind vias will make the board more expensive. And YES. Once a via is assigned to one net, KiCad will not short it to other nets. If you are conducting significant current then I would recommend using multiple vias. (I am conservative in this way.)
If you are willing to share your board layout when you get it done, we might be able to help you to avoid errors if you are willing to post it. Good luck with your project and have fun.
Thank you for your interest regarding my questions,
I have tried to put through-hole vias on the top surface to connect it to the power plane. However, what makes me concerned is even after I set the layer net (by creating a zone and assigning a net to that zone on the inner layer), there is still a rat nest connection between vias and pads. I just wonder is it a normal thing? Below is the a capture of the layout.
There is a limit to what I can tell from your uploaded image. ButâŠnotice that the vias (not just the planes) are assigned to nets. Be sure that all of your individual vias are assigned to the proper nets. Look for the properties of these vias (and then the net) that the rats nest seems to be connecting wrongly. (And check all of your vias.)
One other thingâŠI like to make my tracks almost as wide as the pad that they are connecting to. So for example if a pad is 1 mm wide then I might use a 0.75 or 0.8 mm wide track. I will squeeze them narrower when I need the space. But there are very few situations where a narrower track will work better electrically than a wider one. The narrower track is more easily damaged, it has higher DC resistance, and it has higher inductance. Wider tracks do not increase the cost of the pcb.
Thank you for your reply. Regarding the image that I have shown above, I have already set the net of the vias the same as the net of the power plane. However, there are still rat nest connections that appear for some of the vias, which brought up the concern.
My ultimate goal is to power the power plane (3V3) with a microcontroller pin, and other peripherals on the board would be supplied by that plane. The same idea to the ground, with the final goal of making sure every component is connected to the same ground plane. Would you mind sharing with me a good approach to achieving such goals?
By the way, thank you for the recommendation on increasing the width of the tracks. I would keep that in mind for the design. Thank you very much!
I think I know the problem. I have not filled the solid to the power plane. After I filled all the zones, the rat nest from the via disappeared. Does that mean that everything is good now?
The tracks to C10 are still not wide enough by a margin. The vias @C10 are 1, too far away from the component and 2, unnecessary, because the connection is made at the IC pads. Or - the other way round - the tracks are redundant provided you move the vias close to C10 and C10 closer to the pads.
Anyways should C10 be closer to the pads.
That basically goes for C13 as well.
Not done much/any through hole stuff on KiCAD that needed decoupling . . . how would you stop the pad connecting to the 3.3V plane ? is there an elegant way ?
Off the top of my head: rule area. Cannot be round, though.
But then, I would leave the pads connected and get rid of the vias, move C10 closer to the pads and have at least 16 mils (0.016") tracks to connect it.
Doesnât that mean that the Module (in this case) is going to pull current from the 3.3V plane before it pulls it from the cap ? shouldnât the pin ideally connect to the 3.3V plane after first connecting to the pad with the cap connected ?
I see where youâre heading. But then the cap still suppresses ringing etc. Or at lest I think so.
I rarely do THT and in SMD I always put the vias near the cap and then a trace to the component pad. Iâm talking power here.
However, I am not an expert in board design, not by any means, so maybe someone else can jump in.
I donât think it being very critical. There is no big electric difference between VCC and GND connection. If you have IC with grounded thermal pad you connect it directly to GND plane and not searching first the capacitor GND pin. Do you? May be the (small) capacitance between VCC and GND planes are the capacitor the highest harmonics of current pulses (GHz range) are sourced. And the capacitor (element) itself is only for lower frequencies. Who knows
Thank you for your time and feedback! As a newbie to KiCAD and PCB design, I am really appreciated! I would apply all the recommendations on my PCB design and look forward to having an experienced review when I got it done.
I 100% agree with @BobZ on the use of vias for power. I not only use multiple vias but I increase the hole size (and matching pad diameter).
Iâm not 100% sure but I think inner layers have a default of 0.5 mm (at JPLPCB). You can increase the thickness at the expense of cost.
I couldnât find an actual section of a via, however from the below you can see the connection between the internal planes and the via âtubeâ is not very thick. My information may be a little old but the thickness of the copper in the via diminishes with the depth of the hold and is exacerbated by a small diameter hole.
and that would connect your correctly labeled GND and PWR nets
