Vias: Throughs vs Micros

Several questions related to Multilayer PCBs. Request the enlightened to clear the following:

  1. What is the difference between a via and a Micro (apart from the prime difference that a Through is between the surface layers only)?

  2. Q1 originates from a layout I have been doing today. This is a circuit with a lot of routing and I suspected whther two layers should be enough. I started with a four layered board, consciously reducing the need to go to other layers and ending playing only between F.Cu and In1.Cu. Initially, I found it tough and finally somehow could avoid tracks, components or vias to any other layer. Obviously in the process, I created a number of Micros. I then tried to finish off by swapping the In1.Cuwith B.Cu by just transferring all components to B.Cu from In1.Cu. This is where the questions arise. After the swap, I could see that all tracks got transferred to Even the micros have been changed (their terminal layer changed from In1.Cu to B.Cu wherever needed). But the type of the Via remained to be a Micro

So now, did I need to change all the Via types to “Through”? Can I allow them to remain “Micro”. What difference does it make? To the Gerber and to the manufacturer?

  1. During the DRC, I saw a good number of errors, which were explained with messages starting with an ErrType code. Can someone please help me locate these error codes and their interpretation? (I am aware that the accompanying message also contains sufficient detail, but just wondering if the ErrType codes are a gateway to more information).

  2. Can I have a hole with padding on just one side of the board? I tried to use the Through hole Wire pads but they ended up adding pads on both layers. I need layers on only one.

  3. For placing screws on the corners for example, do I always need to use a Via? Can I indicate it on the board using another method, which does not need electroplating?

  4. When choosing a footprint for a symbol, in the footprint browser, we cannot use the Ruler tool. Is there a plan for the EESchema to allow the Ruler tool on the Footprint selector?

  5. I am loving the PCBNew. But the documentation seems very out of synch with the actual software (5.0.2). How can I help update the observations without affecting the quality?

Please help…


Can’t help with the micro vs through fix up, generally a micro is a partial depth via, vs a through via, which is a plated through hole, micro vias add a lot to the price of PCB’s because it adds a number of extra steps to the manufacturing.

  1. If you have power supplies, that you know are powered, stick a pwr_flag on them, if a pin is set as a power input and does not see a power output out of say a regulator or a pwr_flag it assumes it is not powered, Similar goes for pin conflicts, but these tend to show as warnings

  2. open your footprint in the footprint editor, open a pads properties and untick the layers you want it on, e.g. back copper

  3. You dont actually need to plate mounting holes, you can either use a NPTH (non plated through hole) or a circle on the edge cuts layer for most manufacturers, a plated hole with vias will however reduce how much the epoxy flows away from the mounting pressure of the screw over time. can be solved with a spring washer in a lot of cases,

  4. Submit a bug / feature request on launchpad, lots of things are happening in development now, that sounds reasonably easy to add, but needs an entry to make sure a developer actually acts on it.

  5. What parts have you stuck, I have not reveiwed the documentation in a while, however I would assume it is in the same repository as the code, so suggestions / corrections can be submitted

Thank you. Hpe to act on some of your recommendations in a day or two…

Are you sure? I thought the difference between regular vias and micro vias were the diameter. Micro vias being smaller diameter needing different plating method to reliably connect all the layers (and can potentially be filled). The via types that only go partly through the board I’ve heard called blind and buried.

Or, I’m mistaken…

It’s difficult to find a definitive and exhaustive answer which would eplain everthing, although there is some formal definition:

My understanding at the moment is that micro via is smaller than normal, made (usually? always?) by laser through one laminate structure between two adjacent copper layers. Note the 1:1 restriction. It means that they can connect only copper layers which are very near each other. That restriction would be a natural result of the small diameter.


EDIT 2: where you can see pictures of different micro via setups, stacked and staggered being often mentioned and discussed. It’s also possible to see the conical shape of the via. That’s probably caused by laser burning through the structure. A normal drill wouldn’t do that.

EDIT 3 (and the last one, I promise): More can be found by searching for “microvia laser”.

A through via is available to all layers.
Blind/buried are available to only some layers, and need stack-up care.
Some vendors allow smaller vias in the thinner outer layers only, or are drilled using lasers not drills, which may be what drives micro via naming, as those need separation in any drill file.

I think microvia exists as an easy selection, as I see you can define that as F.Cu to B.Cu if you want to.

Unless you really need Blind/Buried/Micro vias, and are fine with paying the extra cost they impose, you are best to stick with Through Vias.

Any pad can be tagged as NPTH, Mechanical.
That goes into a separate drill file, and is drilled after the plating stage.
Again, you will pay more for the extra handling step, so be sure you really do need it.

The simplest PAD is defined on all copper layers.
It may appear like this in the design file (the design file can give useful hints about what is possible…)
(layers *.Cu *.Mask )

If you want different size on different layers, you declare multiple pads,
This is a mounting hole, the same on all layers np_thru_hole tags as Non plated Thru hole…
(pad "" np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask )

or, if you want a 2 layer stackup, of differing sizes, you create two pads within the component footprint
(pad "" np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers B.Cu B.Mask )
(pad "" np_thru_hole circle (at 0 0) (size 4.2 4.2) (drill 3.2) (layers F.Cu F.Mask )

or even this, for a smaller mask on a larger pad…
(pad "" np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers B.Cu B.Mask )
(pad "" np_thru_hole circle (at 0 0) (size 4.2 4.2) (drill 3.2) (layers F.Cu )
(pad "" np_thru_hole circle (at 0 0) (size 3.7 3.7) (drill 3.2) (layers F.Mask )


Should that layer swap not converting Micros to Vias then be considered a defect by the KiCAD dev team?


Thank you… very helpful examples…

The software may have and does have defects, but please don’t automatically personalize them.

EDIT: after private discussion I understood ventakas meant “considered by dev team”, not “defect by dev team”.


Honestly, I don’t know. I’ve never tried using micro vias.

This topic was automatically closed 90 days after the last reply. New replies are no longer allowed.