Via to pad same net clearance constraint?

[calumet96]

Is there a way to create a custom design rule to check for vias getting too close to pads of the same net? I have looked everywhere and there doesn’t appear to be one.

I don’t know about you all but I’m not comfortable with trusting my vigilance to see if a via gets too close to a pad such that I have to designate to the manufacturer that that via is “via-in-pad” and thereby increase the cost of my board. I avoid via-in-pad unless it’s necessary for thermal or high-density reasons.

The problem is best summed up here: DRC does not report violation if via is placed inside pad (#8472) · Issues · KiCad / KiCad Source Code / kicad · GitLab, unfortunately the suggested workaround (using hole_clearance custom rule) does not appear to work likely because they’re the same net (it works for different nets, I checked).

These are my custom rules - neither of them work for same-nets:

(version 1)

(rule “via_not_in_pad”
(condition “A.Type == ‘via’ && B.Type == ‘pad’”)
(constraint clearance(min 0.01in))
)

(rule “via_not_in_pad2”
(condition “A.Type == ‘via’ && B.Type == ‘pad’”)
(constraint hole_clearance(min 0.01in))
)

Does anyone have any idea how I could write a custom rule to perform this check? I was looking into trying to script something to check it, but the learning curve on scripting with KiCad is a bit steep. I’m guessing I’m going to just have to do that.

[craftyjon]

physical_clearance / physical_hole_clearance are the constraints that operate same-net.

You want:

(rule "via_not_in_pad"
    (condition "A.Type == 'via' && B.Type == 'pad'")
    (constraint physical_hole_clearance (min 0.01in))
    )

[calumet96]

This works! Thank you so much!