I have designed my first PCB. I thought I know enough to faster or slower do what i wont, but I see I was wrong.
PCB was waiting few days. After that I wonted to make gerbers and order it. But before it I run DRC and found all my vias from via stitching lost their connection to GND. So I ordered that PCB without DRC (no time to wait till I will know what to do).
These vias are defined by me footprints (I read here how to do via stitching). Some time passed before I get an idea that I probably done everything right except I didn’t locked my vias, or may be I locked their pad and not the whole footprint (at that moment I don’t know what is enough to be good). There are not a lot of them (simple, small PCB) so I assumed: what I need is only to give each of them GND net and lock - should not take a lot of time. And zonk - I can’t find the way how to do it.
Right mouse click suggests E.
certainly not a place to set GND and lock.
I remember the lesson from my previous question - if you think somesting should be possible and is not use F9. After F9:
I have locked someting. But not sure if pad or the whole footprint. Don’t know how to check it. For devices with few pads I cen poin pad or device. Here I don’t know what I am pointing.
But still don’t know how to set GND. From the above picture I see that E will change Via size. But from ? help I see (last line)
that E will allow me to Edit my via.
I tried E and it made my via smaller (no questions asked). I am surprised as it was not via made during routing but it was defined by me footprint. Did he changed footprint to another (I have 5 different size vias in my library). I don’t know the rule acoording to what that E changes the via size. Trying to use it once more gives me no next changes.
How to lock it to be sure if I locked pad or whole via footprint?
How to set thats via (or may be rather its one pad) net to be GND?
The reason why it does not work is that in kicad vias and traces to not have a net assigned. They get their net from the pad they are connected to. A typical stitching via is not connected via a trace to any pad. This means it will not get a net assigned by the connectivity algorithm. As no net assigned is a different net to your zone it will not connect to the zone. (And zone refill will create a clearance around your via)
In kicad 5 this will be solved. But until then you really need to use the pad workaround.
A workaround for these orphaned vias is to disable “Enforce DRC during routing” option, and then route a track that joins the GND network and these orpahed VIAs. After DR check, these orphaned vias are properly connected to GND network and the ground plane should be solid again. This helped me many times.
I see it is the solution for my problem, but not the way I expected. I have no that PCB here at home to check it.
What in such situation you do with filled zones for the time of routing this tracks joining this vias:
delete it and redefine afterwards,
hide someway (I’m not familiar with interface possibilies yet),
What is the effect if acit is traped (more or less copper left - more as traped acit is not changed by new not used one, less as it stays working there longer than expected)?
If I put via the same way but connect it with the pad using not 10mils track but 20mils you will say it is good?
What if I put the via closer to pad and completely fill this acute angles (connect with track the same size as this pad dimension)?
I frequently have no enough place to put vias farther from pads.
Till now I have never speek with anyone else designing PCB (think like I live at deserted island in that subject). I am doing that way since 20 years and FAB we order prototypes and contract manufacturer (who uses few FABs for our PCBs - their decision which one and why) never questioned my designs. May be it is as I use mainly 10 mils tracks when FAB possibilies are 4/4mils. But it may become very importand if I (don’t plan) use 4/4mils design.
Could you say “If the copper pour has not pulled back from the vias” in the other words. I’m not sure how to understand you. Specially “pulled back from”.
I have done that way (I supposed I had clearly explained it) but probably forgot to lock that footprints (may be I thought that I locked footprints but I locked only their pads - don’t remember) and I am asking “what now”.
No you did not do that. The properties dialog in your screenshot clearly says “via properties” not “pad properties”.
So either you have added a misleading screenshot or you do not fully understand how the workaround is supposed to work.
The prototypes are hand soldered by us (or reflow soldered if too many or too small SMDs - we have oven from times (1996…2004) we produced everything ourselves). Later the same project (prototypes are mainly to work with software not to check hardware so production project is the same as prototype) - we order at contract manufacturer. As we have very few THT they reflow solder SMD and then hand solder THT.
Even if I expect certain project will always be handsoldered by us I design it to allow order externally with no changes. So no vias in pads (except bottom thermal pads), and thermals for zone.
Of course not sure of anything now, but I suppose I undestood how work around works, but made one mistake (I think). Last few days I had no time for enything (now is 4am and I should go to bed), but I will try to make the same mistake just to check it.
While working with PCB everything was good. I put my via, made it being GND (don’t remember how), made a matrix copy of it and then moved one by one to their positions.
Filled zones were filled good and connected to my vias. I finised routing while having PCB opened once (small, simple PCB). Then I saved PCB. When opened after a week the GND disapeared from my vias. All screenshots show how in such situation I am looking how to set this vias once more to GND and to repair my mistake - this are not screenshots made while it was working good.
The acute angle is a sharp V like change, that is an acid trap. When they clean the boards, such sharp v’s can be hard to clean and if all the etchant is not removed, it quietly corrodes the board.
We’e used them for thermal areas, or high current, and they seem to be fine in production.
Some are under tabs of SOT223 parts, and others are in pour planes.
Other CAD pgm allow you to name vias, so choosing from a range of padstacks is easier.
kiCad has only 3 choices. Through/micro/blind-buried
I don’t think I’ve heard much about “acid traps” for a decade or so. They were definitely a concern in the 1990’s, and I have used at least one layout program that specifically flagged acid traps when you ran DRC. A year or two ago somebody - I don’t recall who, or where - told me that current manufacturing methods had eliminated the problems resulting from acid traps. I don’t know if that’s true or not, but I still avoid acute angles when I place tracks, pads, and zones. Perhaps that’s unnecessary effort, but I figure it can’t hurt.
I haven’t worried about solder-filled vias, but it has been a long time since I created a board that was stuffed and soldered on a fully-automated production line. There’s a fear - probably justified - that a via open at both ends will drain solder away from a pad above it. On the other hand, visually inspecting the open end of that via, and noting the amount of solder filling, will give you an idea of how well the solder has flowed on that pad. This can be important when the pad is underneath a large thermal mass, such as a thermal tab.
I extrapolate that idea to most of the geometry constraints a vendor imposes on a board. If he says the minimum via drill is, say, 16 mils (0.4mm) then he is essentially saying, “I can consistently manufacture error-free boards if the hole size never goes below 16 mils.”. What is gained by forcing him to operate at the edge of his capabilities? I’ll call out an 18 mil hole - with a 38 mil pad diameter - and neither of us will worry about broken drill bits, annular ring break-out, drill position accuracy, etc. The same goes for the other geometric limitations, such as minimum trace width and spacing. If he says his product can have feature sizes down to 6 mils, I’ll probably set my design constraints to 8 or 10 mils. Of course, there are occasions when you must claim every mil you can find but in general I try to leave some extra margin.
I can testify to vias robbing solder. I was working on a project for a former university employer where we had to assemble around 2000 (I think we did more to have spares) 1" PMT assemblies. The pre-amplifier boards had vias in some pads, and many of those pads had insufficient solder after the reflow process. (We received them fully assembled from one of the other collaborators.) So it was up to me (and a couple grad students) to inspect each and every board and add solder to suspect points. We didn’t discover this until after the first few batches of assemblies were found to have a high count of failures.
So, it happens. If you put a via in a pad for reflow assembly, please for the sake of everyone downstream from the design phase, engineer methods to ameliorate the effects. Whether that is designing filled vias from the start, or have the stencil apply extra solder paste to those pads, or some other technique I can’t think of. Recognize the possibility and engineer your way around it.
As we have some footprints with predefined vias in the official lib i tried to research this a bit. (I was surprised how much contradictory suggestions about that particular topic is out there.)
My conclusion was that as long as the via is small (drill <= 0.3mm) you normally would not need to worry too much about it. (Just increase the paste coverage a bit and you should be good to go.)
For larger via sizes or if you need higher guarantees you can request your vias to be either filled with plastic or copper. (Both have their unique advantages and disadvantages.)
A cheap option would be to have the via tented. (top and or bottom) tenting the top side is not really easily possible with the settings available in kicad. (There is no negative mask layer.)
So you would need to create a complex soldermask shape on the top side to achieve this. Here it would be beneficial if kicad would support cutting one polygon from another. Sadly this is not supported. So it really gets quite complex. I plan to implement support for this in our footprint generator scripts. (a trivial polygon cutting algorithm is already implemented. But creating a complex top mask layer for exposed pads is not yet implemented)
Vias inside of bga pads are a different story all together. It is a bit out of scope for this discussion. I just want to distinguish it from the handling of normal vias inside of larger pads. (Such that nobody gets the idea that there is never a case where you really have to worry about them)
What size/shape pads & vias were these ?
I’ve never placed vias under 0.5mm TQFP pads for example, only under larger tab type pads.
Given how some parts can have pads that ‘float’ on the reflow and never wet properly, I can see that having a row of small, alike pads where some have flow paths straight down a via-in-pad, could have issues.
Tomb-stoning is a variant of this effect.
One possible approach here could be to use the RS274X plot negative feature (%LPD*%, %LPC*%) ?
I’ve thought that could also provide a means to do the ‘cutout text’ that is often requested for copper fills.
Such variants do need a little user care, as they side-step some of the DRC checks
An easy way to manage that would be via extra layers, that could have some clearly-paired name.
eg F.Cu would have a layer pair called -F.Cu that would negative plot last, into the F,Cu plot file etc.
Not sure where kiCad is up to, with adding user-named layers ?
This is not natively supported by kicad. So it can not be a solution used in the official libs. (Users can do it but the oficial lib is limited by whatever kicad supports out of the box.)
So until somebody can provide convincing evidence that there is a better solution to bottom tented small vias, we will use that for our thermal vias. (As i said above it seems that there is no universal solution to this problem. There is a lot of contradictory information out there. It seems as if every manufacturer wants to sell their premium [= most expensive] solution as the best way to solve this problem)
(Inform me if I am incorrect, so I can withdraw this post.)
“Naively” is a valid word in English, and will be accepted by any spell-check or grammar-check program I know of. However, it gives your sentence a very different meaning. And, being a short, declarative sentence at the beginning of a paragraph it leaves the reader confused - until he steps back and carefully analyzes the most probable intent of the paragraph.