Under constraints, I want to set the Minimum Annular Width=15 mils (for PTH). Under Net Classes, I would like to set my Via Size vs Via Hole size to allow for a much smaller annular ring size.
Does anyone know how I can do this while preventing the Design Rule Checker from flagging annular ring size due to the via annular ring size.
Thanks
PCB Editor / File / Board Setup / Design Rules / Constraints has the setting for the minum annular width:
But are you sure what you are doing? 0.1mm is apparently the default, and that is already pretty thin in my book. If you make this too small, then you seriously impair the manufacturability of your PCB’s. The reason is that drills always have a tolerance in their location. On multi-layer boards it gets even more complicated, because the PCB’s are manufactured with high pressures and hot temperatures, and the layers themselves deform a little bit during manufacturing, and this adds to the final tolerances for the drills.
Oops, scrap that.
When I set KiCad to banana units then it says that the 0.1mm is:
… so you want to make them approximately 4 times bigger 
But that does not rhyme with:
So now I’m confused.
Most cheap boardhouses require 0.15mm (6mil) annular ring width
Global constraints describe the accessible technology. If technology don’t allow for smaller annual width then there is no sense to go in other settings under it.
It looks that you know what you are writing about so it would be easier to understand if you describe the reason you want to design PCB that will be not possible to manufacture with limitations you set yourself as technology parameters.
First, thank you all for jumping in on this.
I design quite a bit with TH components. For those component pins, I want bigger pads (solder/de-solder). If the PTH pads are set too big, I cannot route traces between the pins. Some of the hole sizes are 40 mils+ to accommodate header pins so it’s always a balancing act.
As for vias, depending on whether it’s a power net or signal net, I have more flexibility for sizing when changing layers. Below is a link to one of the pcb houses I use. As you can see, PTH and VIAS have different min/max values. Note: That is a good thing in my book. I love KiCad’s ability to catch my mistakes (I’m just a mere human), but this annular ring “constraint” flag, can generate quite a few errors. I want 15mil min. annular rings on my PTH’s but vias can be less. It compares all annual rings sizes the same i.e., PTH and VIAS.
I was hoping there is a better approach than using “exclusions” under DRC. Too bad there is not a constraint section like uVias that apply to standard vias. I’ve never used “custom rules”, which I plan on reading about.
For example (vias “can” be scaled way down"):
Min. Via hole size/diameter
0.15mm(6mil) / 0.25mm(10mil) <-my default PTH annular ring size of 15mils makes ERC log many errors for the vias.
Look at: Drill/Hole Size and Minimum Annular Ring at the link below.
UPDATE:
I tried using a custom rule with the following:
(version 1)
(rule “VIA”
(constraint hole_size (min 12mil))
(constraint via_diameter (min 20mil))
(condition “A.Type == ‘Via’”))
Unfortunately, this was a waste of time since the pop-up dialog says the constraint overrules these.
If nobody can find a rule based workaround, I would like to push this forward as an enhancement to KiCad. PTH constraints should be different for VIAS. Most pcb mfg’s allow smaller features for vias vs pth. It would also be nice to allow a different clearance requirement when going through plane areas like gnd. This would help prevent swiss cheese reliefs and ensure source & return paths can remain close.
Thanks
Just make yourself sure that in footprint definition you have 15mil and don’t ask KiCad to check it over and over again.
I use default clearance of 0.2mm and for each zone I set 0.25mm clearance. You need more flexibility?
That was my solution, however, having a separate test parameter for regular vias would be helpfull and make the contraints section more consistent.
Thanks, I will use that feature under the plane parameters. I completely forgot this existed.
ERC is a tool to be used for helping us to catch those mistakes that we sometime miss. I use SnapEDA, SamacSys and others for getting starting footprints, symbols and 3D models. I usually make these adjustments but I’m human and sometimes miss the bullseye.
It is not a waste of time to learn custom rules, but you just need to switch the way you are trying to do this.
The constraints section sets the absolute limits, so for things like minimum annular width, it is the smallest you want anywhere on the board.
So, if you want to have some items use a larger annular width, you need to create a custom rule that sets the annular width larger in some cases, and have the smaller value in constraints, not the other way around.
Thanks for the input on what drives the final limit. Maybe I should have not used the word “waste”.
I still maintain it would be more consistent to have the VIA area match that of uVia. The pcb manufacturing limits on each type do vary quite a bit. Most producers of the boards break limits into PTH, VIA & uVIA and can have quite a range of differences.
All that can be accomplished with custom rules. The basic constraints section is not designed to be exhaustive, but rather to capture the most common overall board constraints.
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