It’s a real issue.
I’ve been asked to design very-high-volume boards, where yield is important. Whenever I do those jobs, use the widest traces, biggest spacings, and largest via holes I can. I will lay out the board, and then go back and beef everything up that I can.
Sometimes I increase the VIA size, for instance in power routes.
I really do not see any advantage for that. When you set up your design rules some 20% coarser then what your PCB manufacturer says is their limit, then those rules will be just fine.
That is a really terrible advise. Setup your design rules properly before you start routing, and then stick t those settings. I’ve had PCB’s where I increased track width and/or spacing later, but it soaks up a lot of time to fix such mistakes.
If you design for “very-high-volume” manufacturing, there are other things to consider, such as pad sizes and how it fits with the solder stencil, and how tracks are connected to pads (this can have a significant effect on “tombstoning”). And there are a lot more considerations in “Design for manufacturability”, but you probably know more about DFM then I do.
I’ve been designing boards for 40 years, and I work very closely with a PCB manufacturing house / contract assembler, and this is what they want me to do.
Essential for getting the best yield and minimum production rejects and returns.
This is a different world to hobbyists getting PCBs made by a pool fab
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