I’m unsure of the best format to share for someone who is willing to view it, but here are the Gerber files and a scan of them gerber.rar (148.7 KB).
The issue is that all my vias are the same size, and I’m not sure if I should increase them. For example, I have big traces with small vias, as shown here:
Since I plan to use PCBWay, I followed the guidelines on their website: link.
These are the settings for my vias:
Should I make them bigger? And what should I do with the hole size? How do I know what to set?
I appreciate any input as I am quite new to this.
And also, if someone has input on my board design and can point out any potential issues, I would appreciate the feedback!
two comments; use the back side more, no reason for some of those traces to go to the back side and then come back up just before hitting a hole (which is two sided).
also, no reason to keep all the vias the same size, if you’ve got traces that are carrying a lot of current, then you should calculate the current carrying capabilities of the vias, you might need more than one on some of those traces to switch layers. (isn’t that one of the calculators in kicad?)
edit:
another thought, some of the wide/large current traces can be split into smaller traces with some on top, some on bottom (generally try to keep them mirroring each other).
I thought so too at first. However, this PCB also has zones (only outline shown) so keeping as many of the tracks on the front is good.
For the via’s. You have plenty of room on this PCB. Personally I don’t like small via’s. I would me more inclined to use 1mm via’s with a 0.5mm hole. For high current tracks you can use: PCB Editor / Place / Place Vias [Shift + Ctrl + V] to place multiple via’s on the high current tracks. Apparently it’s common to use 1 via per amp of current but I never checked the validity of that rule of thumb.
I am speaking with hole sizes and not via sizes !
When hole size is decided the via size (diameter) comes from annular ring needed to not hole drilling (un)precision to make it being not entirely inside via copper pad. PCB manufacturers specify minimum annular ring (sometimes different for outer and inner layers).
In 80s it happened (to our PCB manufacturer starting those time) that vias were not plated perfectly. They happened to have no contact, or happened to break with not a big current going through them. The bigger hole the less chance of problems (plating process easier). So I was using 1mm and 0.7mm vias and for current tracks few of them. Later (2000-2010) I was using 0.7mm and 0.5mm vias. When I started to use ICs with thermal pad I decided to use 0.4mm vias and later 0.3mm vias in those pads. Recently (even my contract manufacturer suggested to not do that) I decided to use 0.25mm via as I had very small thermal pad and wanted to have there 4 vias.
Remember you have at start 18um of copper at PCB and 0um in hole. Then during plating copper at PCB rises to 35um while copper in holes rises (at least we hope so) to 18um.
Imagine how these copper atoms have to be placed inside thin hole. If it is done by current flow (I’m not sure, but think so) than that plating rises from via ends and slowly reaches its center (at the beginning there is no copper so no current in the via center). If it works as I think of it (I’m not technologist) then copper in via center is probably thinner than 18um (may be even 2 times).
If you think of current capability you can calculate via as track with width being via circumference and copper thickness of 18um (but I believe it is less).
Currently at PCB I am using vias:
0.9/0.5 - typically,
0.8/0.4 - where I have no space,
1.0/0.6 - as GND planes via stitching.
Smaller vias at my PCBs come only from footprints (thermal pad).
I know my approach is conservative. The highest supply current at my PCBs is 300mA.
