Hello
I’m trying to develop a 4-layer PCB. Since I have some components which must be close together, I’ve set the via properties to “Annular rings: connected layers only”, but they get set back to “Start, end and connected layers”. This reset seems to happen each time the .pcb file is opened.
E.g., if I set the via properties and the save the file, the .pcb file has the line:
(via (at 164.9 90.9) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (remove_unused_layers) (net 1) (tstamp 0406a793-273d-410e-8b92-7440e55b42e5))
After just opening the file in Kicad and saving the file, this line becomes
(via (at 164.9 90.9) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (remove_unused_layers) (keep_end_layers) (net 1) (tstamp 0406a793-273d-410e-8b92-7440e55b42e5))
ie the (keep_end_layers) keeps coming back. Is there any way to stop this? I’m new to PCB design, so maybe what I’m trying to do isn’t sensible.
Thanks