Via properties have no options for solder mask clearance

[ComprehensiveGoose]

I like not tenting vias so they can be used as test points. KiCad has the option to not tent vias in the options for Gerber generation.
Why not add this option to the via properties though? That way one would have control over how small or big the solder mask clearance of a via is, for example (setting solder mask clearance to 0 would result in a tented via). Another benefit of this would be that the 3D viewer would hopefully correctly display vias; currently vias are always shown without a golden annular ring (assuming ENIG, of course).
I know that there are general solder mask settings under “Board Stackup”, which include a setting for “Solder mask to copper clearance” as well as a setting to tent vias. However those settings are very broad and 3D viewer seems to ignore them (when setting vias to not tented they show up tented in the 3D viewer anyway).

One could of course circumvent the issue by creating PTHs instead of using vias. Every PTH pad can be set to a custom solder mask clearance under “Clearance Overrides and Settings”. PTHs show up the 3D viewer correctly as well (the following picture shows a 0.45 mm via (no golden annular ring) next to a 0.45 mm PTH (golden annular ring):

However using a bunch of PTHs just to be in control of solder mask clearance would be a bit overkill.

[eelik]

Part of True padstacks and via stacks with differing geometries on different layers (lp:#1827233) (#2402) · Issues · KiCad / KiCad Source Code / kicad · GitLab

[ComprehensiveGoose]

True pad stacks indeed would also include the option to set values for solder mask clearance:
““Pad Stack” is a term used by PCB layout personnel and PCB fabricators to refer to all of the features associated with a hole in a PCB. The hole can be plated or unplated, through-hole or blind or buried. Components of the pad stack include the drilled hole size, the finished hole size, the size of pads plotted on the inner and outer layers, the clearances in planes through which the holes drilled in the PCB pass, and the clearances in the solder mask applied to the outer layers of the PCB.”

That the 3D viewer currently is displaying untented vias wrongly is of course another issue.

[BlackCoffee]

If you click the Green Icon at top left of the PCB editor, you get Pref’s panel that contains Checkbox for Tenting Vias…

[ComprehensiveGoose]

I know. The problem with this setting is that a) the KiCad 3D Viewer completely ignores it and b) one cannot give vias a clearance of for example 80 µm (while everything else, as per your settings, would get a clearance of 51 µm.