Would someone tell me how to get the PCB made with vias getting plated?
I found that the vias on the board that I designed and made by or through DirtyPCB.com do not get plated with solder at all. Is this a nornal or default result by KiCad? Or I need to do something about it within KiCad to get them plated?
I would think plated vias can have less resistance than the not-placed ones.
FYI, I’ve been using the most recent development versions of KiCad that is built and installed in my Linux PCs.
Do you mean you don’t have any conductivity through the vias? Your board must be ruined then, I would think it is a manufacturing problem. Not plating vias kind of defies the purpose of having them at all…
Usually if you have copper under the via, it should get plated - at least that is how OSHpark identifies plated and unplated vias(drill with copper under or above the hole —> plated). Can you post a picture (pcbnew screenshot) of a via that was not plated with all copper layers turned on?
I meant to say “tinned” vias. The PCBs are not bad at all since vias are indeed copper plated, and I measured some of them and there is indeed a conductivity through the vias.
But I was surprised by the un-tinned vias of my 2-layer PCBs. Now I know why. It’s KiCad that sets this way by default when plotting the gerber files.
If you want to have vias tinned like regular through holes, ( I know I do), you need to put a check mark on “Do not tent vias” within the pop-up window after clicking “File->Plot”. I only found this out after inspecting the solder masks of with and without the option.