Is this something that the board layout is supposed to specify? (i.e., information that the Gerbers are supposed to embed?)
Or is it typically done through some “ad hoc” communication with the manufacturer, somewhat “manually” indicating which vias are supposed to be filled, and with a copper+finish pad placed on top? If so, do I simply place the via inside the SMT pad?
My understanding is that if I place a via inside an SMT pad, that will end up producing exactly the same actual/physical outcome as a THT pad — but then, maybe KiCAD treats it differently? (after all, it sees that there an SMT pad, and it sees that the hole is a via, and not the hole in a THT pad)
You can’t easily specify this in many ECAD tools (including KiCad). Instead you typically instruct the manufacturer “vias of diameter X inside pads are to be filled and then capped/plated”
If you only need certain vias filled (and cannot distinguish them by drill size or something simple) you will need a drawing where you give them a special symbol or something, and the fabricator will work from that drawing. But as far as I know, it is always a process involving human review, there is no automated way to set it up in a Gerber that will avoid the need for some conversation.
If you want via-in-pad, you’d probably be better of by selecting and contacting a manufacturer before you design the PCB. That way you can design in any special settings they may want from your part, so you do not have to redo those.
KiCad Gerbers indicate which drill tools are via’s and which pads are SMD using attributes in the Gerbers. (In X2 with commands, in good old 274X with standardized comments.) And via-in-pad must be filled and plated. It is unequivocal.
This being said, paulvdh is right that it is best to explicitly warn the fabricator.
This is not really true: vias-in-pads must only be filled and plated if (a) there is solder paste on that pad, and (b) the proportion of the finished via hole size to the pad size means that solder paste wicking is likely to be a concern. Thermal vias inside the exposed pads of larger surface-mount packages generally don’t need to be filled, for example.
(this is the usual reason for filling: there may be more rare reasons for filling that are unrelated to solder paste wicking)
We use via in pad extensively. It is not automatic that a via in pad will be filled and plated. This must be specified to the PCB fabricator.
As discussed above, we use a specific via diameter for those vias, which is usually the smallest via we use on a PCB. For work, we use Altium, but there is no way to specify this, so we include it in our fab notes. It seems a pretty big oversight, but there it is…
FWIW, a filled and plated/copper capped via is an IPC Type VII via. I just learned this a few months ago by accident, after using them for quite some years.
My back of the envelope calculation comes to about 10x the resistance for the conductive epoxy filling compared to the via plating copper. Are you sure this is worth it? Maybe you can fit a THT component with thick leads instead?
Not sure what level of boards your are talking about (i.e. Chinese hobby, commercial, military etc) but I would think the larger the via hole the better the conductivity. For my hobby boards I routinely use multiple vias where any significant amount of current is require.
I believe 1 oz/ft^2 boards are 0.7 oz/ft^2 plated to 1. This makes the via walls (at best) 0.3 oz/f^2.
I wonder with the SI units are for plating weight.
The via attribute in the Gerber spec has an optional field Filled|NotFilled to the via attribute. However, as far as I know there is no way to convince KiCad to set that option. Brave (or reckless) ones may edit the Gerber file with a text editor…
However, the Gerber job file allows to speficy via filling, even the IPC Type. Pretty good.
“Covered” seems to be a counterpart, or an alternative, to “tented” and also to “capped”. I don’t know what to make of that.
So: what is the difference between “tented” and “covered”? What does cover mean in type VI? (i.e., covered as opposed to capped)
If “filled” means “fully plugged”, then what does “(non-fully) plugged” mean? (sounds like just covering the plating inside the via with soldermask, but without the requirement that the whole volume/space inside the via gets filled? is that a thing? I guess for large vias the distinction would make sense)
BTW, at this point, my questions are purely personal curiosity; I guess knowing those is not going to be relevant for any of my projects (hobby or work-related)
Yup that confirms my suspicion, Dave is using 60/40 solder to fill the via, which has about 15µOhmcm volumetric resistance, CB100 filling has 160µOhmcm[1], so the effect of conductive epoxy is going to be about 1/10th compared to filling it with solder. I’d expect no more than a 5-10% improvement on a huge 1.1mm via, on smaller ones even less, because the plated copper resistance scales with 1/R, and the filling scales with 1/R². Conductive filling is rarely done, and usually only for better thermal conductivity.
[1] http://allenwoodsgroup.com/pdf/TATSUTAAE3030.pdf
The meaning is explained in excruciating detail in the IPC-4761 specification. This is the beauty of specs! Less beautiful is that you must pay for IPC specs, and they are not really cheap.
However, a quick Google search brought up plenty of documents with explanations.
